On Thu, May 28, 2015 at 10:39 AM, Alan Modra <amo...@gmail.com> wrote:
> The problem is that the following testcase on powerpc64le now
> generates worse code.
>
> void foo (signed char *p) { if (*p != 0) *p = 1; }
>
> before after
> foo: foo:
> lbz 9,0(3) lbz 9,0(3)
> cmpwi 7,9,0 andi. 10,9,0xff
> beqlr 7 beqlr 0
> li 9,1 li 9,1
> stb 9,0(3) stb 9,0(3)
> blr blr
>
> That record form andi. is slower on many processors, and restricted to
> setting cr0.
> allowing combination of insns 6, 7 and 8
> original costs 8 + 4 + 4 = 16
> replacement costs 8 + 4 = 12
> Does anyone have any clues as to how I might fix this? I'm not keen
> on adding an insn_and_split to rs6000.md to recognize the 6 -> 8
> combination, because one of the aims of the wider patch I was working
> on was to remove patterns like rotlsi3_64, ashlsi3_64, lshrsi3_64 and
> ashrsi3_64. Adding patterns in order to remove others doesn't sound
> like much of a win.
This seems like a problem with the cost model. Rc instructions are
more expensive and should be represented as such in rtx_costs.
- David
