Hi All,
I am porting gcc for an internal processor and I am having some issues with
math instructions. Our processor uses two operands for math instructions which
are usually of the form OP0 = OP0 + OP1. The RTL pattern (for addm3) in gcc
uses the form OP0 = OP1 + OP2. I understand that gcc supposedly supports the
two operand flavor, but I have not been able to convince it to do that for me.
I tried the following RTL pattern with no success:
(define_insn "addhi3_op1_is_op0"
[(set (match_operand:HI 0 "register_operand" "=a")
(plus:HI (match_dup 0)
(match_operand:HI 1 "general_operand" "aim")))]
""
{
output_asm_insn("//Start of addhi3_op1_is_op0 %0 = %1 + %2", operands);
output_asm_insn("//End of addhi3_op1_is_op0", operands);
return("");
}
)
So I used the three operand form and fixed things up in the code:
(define_insn "addhi3_regtarget"
[(set (match_operand:HI 0 "register_operand" "=a")
(plus:HI (match_operand:HI 1 "general_operand" "aim")
(match_operand:HI 2 "general_operand" "aim")))]
""
{
output_asm_insn("//Start of addhi3_regtarget %0 = %1 + %2", operands);
snap_do_basic_math_op_hi(operands, MATH_OP_PLUS);
output_asm_insn("//End of addhi3_regtarget", operands);
return("");
}
)
Of course this does not work for all cases since my fixup cannot detect if the
operands are the same memory location for OP0 and either OP1 or OP2. So I am
back to trying to find the right RTL magic to do this right. I have looked
over a number of machine descriptions but have not been able to find the
precise pattern for this.
Any help is greatly appreciated.
Steve Silva (Broadcom)
