Hello, I'm a newbie working on a GCC port [1] for PRU [2]. In order to achieve ABI compatibility with the proprietary TI toolchain, I need my Machine Description to support HW register subfields as indipendent first-class registers. I could not find a relevant example in the GCC source. Looks like other ports declare subregisters to be the same entities as the corresponding main register (e.g. %al , %ah and %ax are treated by the GCC register allocator as one and same i386 register).
So is it possible to describe subregs (independent fields) of 32-bit HW registers in GCC? Currently I'm attempting to describe the 8-bit PRU subregisters as the "real" target register set, and then work on defining 16-bit and 32-bit ALU operations. But I'm not sure if that would be efficient for a 32-bit PRU target, or feasible at all. To give an example, each 32-bit PRU register can hold either: - one 32-bit value (e.g. r10) - four independent 8-bit values (e.g. r10.b0, r10.b1, r10.b2, r10.b3). - two independent 16-bit values (e.g. r10.w0, r10.w2). - a mixture of the above (e.g. r10.w0, r10.b2, r10.b3). And here is an example of zero-extending one 8-bit and one 16-bit value, performing a 32-bit addition, and storing the result into another 8-bit subregister: add r10.b3, r10.b2, r10.w0 Thanks, Dimitar [1] https://github.com/dinuxbg/gnupru/tree/master/patches/gcc [2] http://elinux.org/images/d/da/Am335xPruReferenceGuide.pdf , section 5.3.2.5.2 "Registers"
