On Thu, Nov 1, 2018 at 10:42 AM Joern Wolfgang Rennecke
<joern.renne...@riscy-ip.com> wrote:
>
>
> On 30/10/18 08:36, Richard Biener wrote:
> > On Mon, Oct 29, 2018 at 7:03 PM Joern Wolfgang Rennecke
> > <joern.renne...@riscy-ip.com> wrote:
> >> I want to submit some vectorizer patches, what would be a suitable
> >> regression test?
> > I am sure you have testcases, no? For new features please make them
> > dg-do run ones by checking correctness.
> For the dot product / widen_sum -> madd transformations to trigger,
> I need an in-tree port with a named pattern matched by
> smadd_widen_optab or umadd_widen_optab, with an input matching
> PREFERRED_SIMD_VECTOR_MODE, and hence an output twice that
> size (and that pattern must not be eclipsed by existing
> [us]sum_widen_optab and [us]dot_prod_optab matches).
>
> I can't find any such port in the tree. Indeed, not any
> {u,}madd<vector_in_mode><vector_out_mode>4 pattern at all.
>
> I've heard that arm cortex-m4 hardware acctually supports a madd vector
> operation
> (V2HI -> V2SI), is that true?
Don't think there's a single instruction that does that.
smlad is the closest IIRC and checking with the Arm ARM, that's V2HI
-> V2HI for the multiplication and then an accumulation with a 32 bit
accumulator. Thus effectively a add (reduc_add (mult(v2hi , v2hi)),
si) , but we don't support any vector forms using the integer register
set for the M profile architecture as of today in gcc. Thus you
probably need 2 smlald instructions to achieve this IIUC . We do have
a dot product optab in the arm backend but that's with Advanced simd
which isn't in the M profile.
regards
Ramana
>
> Would the test be suitable if it made the arm target,
> with a patch added to add a suitable madd pattern, and my vectorizer
> patch added,
> use that madd pattern?
>
> Or could I add an imaginary madd vector extension instruction to the arc for
> that purpose? But then, it wouldn't actually execute, as it's just a
> made-up instruction;
> nor would the vectorization test be included in a test run for an actual.
