Hi, On Wed, 13 Feb 2019, Peng Fan wrote:
> asm volatile ( > "ldxr %3, %2\n\t" > "ands %1, %3, %4\n\t" > "b.ne 1f\n\t" > "orr %3, %3, %4\n\t" > "1:\n\t" > "stxr %w0, %3, %2\n\t" > "dmb ish\n\t" > : "=r" (ret), "=&r" (test), > "+Q" (*(volatile unsigned long *)addr), > "=r" (tmp) > : "r" (1ul << nr)); As Andreas says, you need to add an early-clobber for op3 for correctness (to force it into a different register from op4). And you also need an early-clobber on op0 to force it into a different register from op2 (which for purposes of register assignment is an input operand holding an address). Ciao, Michael.
