Here is the cpuid output
On 29/12/2019 22:57, Even Rouault wrote:
On dimanche 29 décembre 2019 22:36:24 CET Momtchil Momtchev wrote:
Disabling HAVE_SSSE3_AT_COMPILE_TIME had no effect,
Make sure you run "make clean" after running ./configure
but after
short-circuiting the #ifdef I got a correct result.
Hum so it seems that the SSSE3 detection doesn't work properly.
Can you :
1. undo your code changes
2. modify port/cpl_cpu_features.cpp at line 98 to replace the code of the
CPLDetectSSE3() function by
static inline bool CPLDetectSSE3()
{
int cpuinfo[4] = { 0, 0, 0, 0 };
CPL_CPUID(0, cpuinfo);
if( cpuinfo[REG_EAX] <= 0 )
return false;
CPL_CPUID(1, cpuinfo);
return (cpuinfo[REG_ECX] & (1 << CPUID_SSSE3_ECX_BIT)) != 0;
}
(note: this function should really be called CPLDetectSSSE3 ... missing S...
but that doesn't matter)
3. modify port/cpl_cpu_features.h to add just after line 47 "#if __SSSE3__" a
new line with "dummy" as content. Normally this shouldn't be compiled... but
this is just to make sure the compiler doesn't define SSSE3 as available
unconditionnally at runtime.
4. run configure again *without* disabling ssse3
5. make clean
6. make (possibly with -j something)
--
Momtchil Momtchev <[email protected]>
CPU 0:
vendor_id = "AuthenticAMD"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium 4/Pentium D/Pentium Extreme
Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon
XP-M/Opteron/Sempron/Turion (15)
model = 0x4 (4)
stepping id = 0x3 (3)
extended family = 0x1 (1)
extended model = 0x0 (0)
(simple synth) = AMD Phenom II (Callisto / Heka / Deneb RB-C3) [K10],
45nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
cpu count = 0x4 (4)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = false
ACPI: thermal monitor and clock ctrl = false
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = false
hyper-threading / multi-core supported = true
TM: therm. monitor = false
IA64 = false
PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = false
DTES64: 64-bit debug store = false
MONITOR/MWAIT = true
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
TM2: thermal monitor 2 = false
SSSE3 extensions = false
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = false
PDCM: perfmon and debug = false
PCID: process context identifiers = false
DCA: direct cache access = false
SSE4.1 extensions = false
SSE4.2 extensions = false
x2APIC: extended xAPIC support = false
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = false
AES instruction = false
XSAVE/XSTOR states = false
OS-enabled XSAVE/XSTOR = false
AVX: advanced vector extensions = false
F16C half-precision convert instruction = false
RDRAND instruction = false
hypervisor guest status = false
cache and TLB information (2):
processor serial number: 0010-0F43-0000-0000-0000-0000
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
extended processor signature (0x80000001/eax):
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
model = 0x4 (4)
stepping id = 0x3 (3)
extended family = 0x1 (1)
extended model = 0x0 (0)
(simple synth) = AMD Phenom II (Callisto / Heka / Deneb RB-C3) [K10], 45nm
extended feature flags (0x80000001/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSCALL and SYSRET instructions = true
memory type range registers = true
global paging extension = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
multiprocessing capable = false
no-execute page protection = true
AMD multimedia instruction extensions = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
1-GB large page support = true
RDTSCP = true
long mode (AA-64) = true
3DNow! instruction extensions = true
3DNow! instructions = true
extended brand id (0x80000001/ebx):
raw = 0x10001c16 (268442646)
BrandId = 0x1c16 (7190)
str1 = 0x3 (3)
str2 = 0x6 (6)
PartialModel = 0x41 (65)
PG = 0x0 (0)
PkgType = 0x1 (1)
AMD feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
CMP Legacy = true
SVM: secure virtual machine = true
extended APIC space = true
AltMovCr8 = true
LZCNT advanced bit manipulation = true
SSE4A support = true
misaligned SSE mode = true
3DNow! PREFETCH/PREFETCHW instructions = true
OS visible workaround = true
instruction based sampling = true
XOP support = false
SKINIT/STGI support = true
watchdog timer support = true
lightweight profiling support = false
4-operand FMA instruction = false
TCE: translation cache extension = false
NodeId MSR C001100C = false
TBM support = false
topology extensions = false
core performance counter extensions = false
data breakpoint extension = false
performance time-stamp counter support = false
performance counter extensions = false
MWAITX/MONITORX supported = false
brand = "AMD Phenom(tm) II X4 965 Processor"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x10 (16)
instruction associativity = 0xff (255)
data # entries = 0x30 (48)
data associativity = 0xff (255)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x20 (32)
instruction associativity = 0xff (255)
data # entries = 0x30 (48)
data associativity = 0xff (255)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (KB) = 0x40 (64)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (KB) = 0x40 (64)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x80 (128)
data associativity = 2-way (2)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x200 (512)
instruction associativity = 4-way (4)
data # entries = 0x200 (512)
data associativity = 4-way (4)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 16-way (8)
size (KB) = 0x200 (512)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 48-way (11)
size (in 512KB units) = 0xc (12)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = true
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = true
TM: thermal monitor = true
STC: software thermal control = true
100 MHz multiplier control = true
hardware P-State control = true
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x30 (48)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x3 (3)
ApicIdCoreIdSize = 0x2 (2)
SVM Secure Virtual Machine (0x8000000a/eax):
SvmRev: SVM revision = 0x1 (1)
SVM Secure Virtual Machine (0x8000000a/edx):
nested paging = true
LBR virtualization = true
SVM lock = true
NRIP save = true
MSR based TSC rate control = false
VMCB clean bits support = false
flush by ASID = false
decode assists = false
SSSE3/SSE5 opcode set disable = false
pause intercept filter = false
pause filter threshold = false
AVIC: AMD virtual interrupt controller = false
virtualized VMLOAD/VMSAVE = false
virtualized GIF = false
NASID: number of address space identifiers = 0x40 (64):
L1 TLB information: 1G pages (0x80000019/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x30 (48)
data associativity = full (15)
L2 TLB information: 1G pages (0x80000019/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x10 (16)
data associativity = 8-way (6)
SVM Secure Virtual Machine (0x8000001a/eax):
128-bit SSE executed full-width = true
MOVU* better than MOVL*/MOVH* = true
256-bit SSE executed full-width = false
Instruction Based Sampling Identifiers (0x8000001b/eax):
IBS feature flags valid = true
IBS fetch sampling = true
IBS execution sampling = true
read write of op counter = true
op counting mode = true
branch target address reporting = false
IbsOpCurCnt and IbsOpMaxCnt extend 7 = false
invalid RIP indication support = false
fused branch micro-op indication support = false
IBS fetch control extended MSR support = false
IBS op data 4 MSR support = false
(instruction supported synth):
CMPXCHG8B = true
conditional move/compare = true
PREFETCH/PREFETCHW = true
(multi-processing synth): multi-core (c=4)
(multi-processing method): AMD
(APIC widths synth): CORE_width=2 SMT_width=0
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(synth) = AMD Phenom II X4 (Deneb RB-C3) [K10], 45nm 965 Processor
CPU 1:
vendor_id = "AuthenticAMD"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium 4/Pentium D/Pentium Extreme
Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon
XP-M/Opteron/Sempron/Turion (15)
model = 0x4 (4)
stepping id = 0x3 (3)
extended family = 0x1 (1)
extended model = 0x0 (0)
(simple synth) = AMD Phenom II (Callisto / Heka / Deneb RB-C3) [K10],
45nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x1 (1)
cpu count = 0x4 (4)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = false
ACPI: thermal monitor and clock ctrl = false
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = false
hyper-threading / multi-core supported = true
TM: therm. monitor = false
IA64 = false
PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = false
DTES64: 64-bit debug store = false
MONITOR/MWAIT = true
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
TM2: thermal monitor 2 = false
SSSE3 extensions = false
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = false
PDCM: perfmon and debug = false
PCID: process context identifiers = false
DCA: direct cache access = false
SSE4.1 extensions = false
SSE4.2 extensions = false
x2APIC: extended xAPIC support = false
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = false
AES instruction = false
XSAVE/XSTOR states = false
OS-enabled XSAVE/XSTOR = false
AVX: advanced vector extensions = false
F16C half-precision convert instruction = false
RDRAND instruction = false
hypervisor guest status = false
cache and TLB information (2):
processor serial number: 0010-0F43-0000-0000-0000-0000
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
extended processor signature (0x80000001/eax):
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
model = 0x4 (4)
stepping id = 0x3 (3)
extended family = 0x1 (1)
extended model = 0x0 (0)
(simple synth) = AMD Phenom II (Callisto / Heka / Deneb RB-C3) [K10], 45nm
extended feature flags (0x80000001/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSCALL and SYSRET instructions = true
memory type range registers = true
global paging extension = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
multiprocessing capable = false
no-execute page protection = true
AMD multimedia instruction extensions = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
1-GB large page support = true
RDTSCP = true
long mode (AA-64) = true
3DNow! instruction extensions = true
3DNow! instructions = true
extended brand id (0x80000001/ebx):
raw = 0x10001c16 (268442646)
BrandId = 0x1c16 (7190)
str1 = 0x3 (3)
str2 = 0x6 (6)
PartialModel = 0x41 (65)
PG = 0x0 (0)
PkgType = 0x1 (1)
AMD feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
CMP Legacy = true
SVM: secure virtual machine = true
extended APIC space = true
AltMovCr8 = true
LZCNT advanced bit manipulation = true
SSE4A support = true
misaligned SSE mode = true
3DNow! PREFETCH/PREFETCHW instructions = true
OS visible workaround = true
instruction based sampling = true
XOP support = false
SKINIT/STGI support = true
watchdog timer support = true
lightweight profiling support = false
4-operand FMA instruction = false
TCE: translation cache extension = false
NodeId MSR C001100C = false
TBM support = false
topology extensions = false
core performance counter extensions = false
data breakpoint extension = false
performance time-stamp counter support = false
performance counter extensions = false
MWAITX/MONITORX supported = false
brand = "AMD Phenom(tm) II X4 965 Processor"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x10 (16)
instruction associativity = 0xff (255)
data # entries = 0x30 (48)
data associativity = 0xff (255)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x20 (32)
instruction associativity = 0xff (255)
data # entries = 0x30 (48)
data associativity = 0xff (255)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (KB) = 0x40 (64)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (KB) = 0x40 (64)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x80 (128)
data associativity = 2-way (2)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x200 (512)
instruction associativity = 4-way (4)
data # entries = 0x200 (512)
data associativity = 4-way (4)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 16-way (8)
size (KB) = 0x200 (512)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 48-way (11)
size (in 512KB units) = 0xc (12)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = true
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = true
TM: thermal monitor = true
STC: software thermal control = true
100 MHz multiplier control = true
hardware P-State control = true
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x30 (48)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x3 (3)
ApicIdCoreIdSize = 0x2 (2)
SVM Secure Virtual Machine (0x8000000a/eax):
SvmRev: SVM revision = 0x1 (1)
SVM Secure Virtual Machine (0x8000000a/edx):
nested paging = true
LBR virtualization = true
SVM lock = true
NRIP save = true
MSR based TSC rate control = false
VMCB clean bits support = false
flush by ASID = false
decode assists = false
SSSE3/SSE5 opcode set disable = false
pause intercept filter = false
pause filter threshold = false
AVIC: AMD virtual interrupt controller = false
virtualized VMLOAD/VMSAVE = false
virtualized GIF = false
NASID: number of address space identifiers = 0x40 (64):
L1 TLB information: 1G pages (0x80000019/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x30 (48)
data associativity = full (15)
L2 TLB information: 1G pages (0x80000019/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x10 (16)
data associativity = 8-way (6)
SVM Secure Virtual Machine (0x8000001a/eax):
128-bit SSE executed full-width = true
MOVU* better than MOVL*/MOVH* = true
256-bit SSE executed full-width = false
Instruction Based Sampling Identifiers (0x8000001b/eax):
IBS feature flags valid = true
IBS fetch sampling = true
IBS execution sampling = true
read write of op counter = true
op counting mode = true
branch target address reporting = false
IbsOpCurCnt and IbsOpMaxCnt extend 7 = false
invalid RIP indication support = false
fused branch micro-op indication support = false
IBS fetch control extended MSR support = false
IBS op data 4 MSR support = false
(instruction supported synth):
CMPXCHG8B = true
conditional move/compare = true
PREFETCH/PREFETCHW = true
(multi-processing synth): multi-core (c=4)
(multi-processing method): AMD
(APIC widths synth): CORE_width=2 SMT_width=0
(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
(synth) = AMD Phenom II X4 (Deneb RB-C3) [K10], 45nm 965 Processor
CPU 2:
vendor_id = "AuthenticAMD"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium 4/Pentium D/Pentium Extreme
Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon
XP-M/Opteron/Sempron/Turion (15)
model = 0x4 (4)
stepping id = 0x3 (3)
extended family = 0x1 (1)
extended model = 0x0 (0)
(simple synth) = AMD Phenom II (Callisto / Heka / Deneb RB-C3) [K10],
45nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x2 (2)
cpu count = 0x4 (4)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = false
ACPI: thermal monitor and clock ctrl = false
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = false
hyper-threading / multi-core supported = true
TM: therm. monitor = false
IA64 = false
PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = false
DTES64: 64-bit debug store = false
MONITOR/MWAIT = true
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
TM2: thermal monitor 2 = false
SSSE3 extensions = false
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = false
PDCM: perfmon and debug = false
PCID: process context identifiers = false
DCA: direct cache access = false
SSE4.1 extensions = false
SSE4.2 extensions = false
x2APIC: extended xAPIC support = false
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = false
AES instruction = false
XSAVE/XSTOR states = false
OS-enabled XSAVE/XSTOR = false
AVX: advanced vector extensions = false
F16C half-precision convert instruction = false
RDRAND instruction = false
hypervisor guest status = false
cache and TLB information (2):
processor serial number: 0010-0F43-0000-0000-0000-0000
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
extended processor signature (0x80000001/eax):
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
model = 0x4 (4)
stepping id = 0x3 (3)
extended family = 0x1 (1)
extended model = 0x0 (0)
(simple synth) = AMD Phenom II (Callisto / Heka / Deneb RB-C3) [K10], 45nm
extended feature flags (0x80000001/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSCALL and SYSRET instructions = true
memory type range registers = true
global paging extension = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
multiprocessing capable = false
no-execute page protection = true
AMD multimedia instruction extensions = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
1-GB large page support = true
RDTSCP = true
long mode (AA-64) = true
3DNow! instruction extensions = true
3DNow! instructions = true
extended brand id (0x80000001/ebx):
raw = 0x10001c16 (268442646)
BrandId = 0x1c16 (7190)
str1 = 0x3 (3)
str2 = 0x6 (6)
PartialModel = 0x41 (65)
PG = 0x0 (0)
PkgType = 0x1 (1)
AMD feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
CMP Legacy = true
SVM: secure virtual machine = true
extended APIC space = true
AltMovCr8 = true
LZCNT advanced bit manipulation = true
SSE4A support = true
misaligned SSE mode = true
3DNow! PREFETCH/PREFETCHW instructions = true
OS visible workaround = true
instruction based sampling = true
XOP support = false
SKINIT/STGI support = true
watchdog timer support = true
lightweight profiling support = false
4-operand FMA instruction = false
TCE: translation cache extension = false
NodeId MSR C001100C = false
TBM support = false
topology extensions = false
core performance counter extensions = false
data breakpoint extension = false
performance time-stamp counter support = false
performance counter extensions = false
MWAITX/MONITORX supported = false
brand = "AMD Phenom(tm) II X4 965 Processor"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x10 (16)
instruction associativity = 0xff (255)
data # entries = 0x30 (48)
data associativity = 0xff (255)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x20 (32)
instruction associativity = 0xff (255)
data # entries = 0x30 (48)
data associativity = 0xff (255)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (KB) = 0x40 (64)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (KB) = 0x40 (64)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x80 (128)
data associativity = 2-way (2)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x200 (512)
instruction associativity = 4-way (4)
data # entries = 0x200 (512)
data associativity = 4-way (4)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 16-way (8)
size (KB) = 0x200 (512)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 48-way (11)
size (in 512KB units) = 0xc (12)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = true
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = true
TM: thermal monitor = true
STC: software thermal control = true
100 MHz multiplier control = true
hardware P-State control = true
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x30 (48)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x3 (3)
ApicIdCoreIdSize = 0x2 (2)
SVM Secure Virtual Machine (0x8000000a/eax):
SvmRev: SVM revision = 0x1 (1)
SVM Secure Virtual Machine (0x8000000a/edx):
nested paging = true
LBR virtualization = true
SVM lock = true
NRIP save = true
MSR based TSC rate control = false
VMCB clean bits support = false
flush by ASID = false
decode assists = false
SSSE3/SSE5 opcode set disable = false
pause intercept filter = false
pause filter threshold = false
AVIC: AMD virtual interrupt controller = false
virtualized VMLOAD/VMSAVE = false
virtualized GIF = false
NASID: number of address space identifiers = 0x40 (64):
L1 TLB information: 1G pages (0x80000019/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x30 (48)
data associativity = full (15)
L2 TLB information: 1G pages (0x80000019/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x10 (16)
data associativity = 8-way (6)
SVM Secure Virtual Machine (0x8000001a/eax):
128-bit SSE executed full-width = true
MOVU* better than MOVL*/MOVH* = true
256-bit SSE executed full-width = false
Instruction Based Sampling Identifiers (0x8000001b/eax):
IBS feature flags valid = true
IBS fetch sampling = true
IBS execution sampling = true
read write of op counter = true
op counting mode = true
branch target address reporting = false
IbsOpCurCnt and IbsOpMaxCnt extend 7 = false
invalid RIP indication support = false
fused branch micro-op indication support = false
IBS fetch control extended MSR support = false
IBS op data 4 MSR support = false
(instruction supported synth):
CMPXCHG8B = true
conditional move/compare = true
PREFETCH/PREFETCHW = true
(multi-processing synth): multi-core (c=4)
(multi-processing method): AMD
(APIC widths synth): CORE_width=2 SMT_width=0
(APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
(synth) = AMD Phenom II X4 (Deneb RB-C3) [K10], 45nm 965 Processor
CPU 3:
vendor_id = "AuthenticAMD"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium 4/Pentium D/Pentium Extreme
Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon
XP-M/Opteron/Sempron/Turion (15)
model = 0x4 (4)
stepping id = 0x3 (3)
extended family = 0x1 (1)
extended model = 0x0 (0)
(simple synth) = AMD Phenom II (Callisto / Heka / Deneb RB-C3) [K10],
45nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x3 (3)
cpu count = 0x4 (4)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = false
ACPI: thermal monitor and clock ctrl = false
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = false
hyper-threading / multi-core supported = true
TM: therm. monitor = false
IA64 = false
PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = false
DTES64: 64-bit debug store = false
MONITOR/MWAIT = true
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
TM2: thermal monitor 2 = false
SSSE3 extensions = false
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = false
PDCM: perfmon and debug = false
PCID: process context identifiers = false
DCA: direct cache access = false
SSE4.1 extensions = false
SSE4.2 extensions = false
x2APIC: extended xAPIC support = false
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = false
AES instruction = false
XSAVE/XSTOR states = false
OS-enabled XSAVE/XSTOR = false
AVX: advanced vector extensions = false
F16C half-precision convert instruction = false
RDRAND instruction = false
hypervisor guest status = false
cache and TLB information (2):
processor serial number: 0010-0F43-0000-0000-0000-0000
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
extended processor signature (0x80000001/eax):
family/generation = AMD Athlon 64/Opteron/Sempron/Turion (15)
model = 0x4 (4)
stepping id = 0x3 (3)
extended family = 0x1 (1)
extended model = 0x0 (0)
(simple synth) = AMD Phenom II (Callisto / Heka / Deneb RB-C3) [K10], 45nm
extended feature flags (0x80000001/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSCALL and SYSRET instructions = true
memory type range registers = true
global paging extension = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
multiprocessing capable = false
no-execute page protection = true
AMD multimedia instruction extensions = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
1-GB large page support = true
RDTSCP = true
long mode (AA-64) = true
3DNow! instruction extensions = true
3DNow! instructions = true
extended brand id (0x80000001/ebx):
raw = 0x10001c16 (268442646)
BrandId = 0x1c16 (7190)
str1 = 0x3 (3)
str2 = 0x6 (6)
PartialModel = 0x41 (65)
PG = 0x0 (0)
PkgType = 0x1 (1)
AMD feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
CMP Legacy = true
SVM: secure virtual machine = true
extended APIC space = true
AltMovCr8 = true
LZCNT advanced bit manipulation = true
SSE4A support = true
misaligned SSE mode = true
3DNow! PREFETCH/PREFETCHW instructions = true
OS visible workaround = true
instruction based sampling = true
XOP support = false
SKINIT/STGI support = true
watchdog timer support = true
lightweight profiling support = false
4-operand FMA instruction = false
TCE: translation cache extension = false
NodeId MSR C001100C = false
TBM support = false
topology extensions = false
core performance counter extensions = false
data breakpoint extension = false
performance time-stamp counter support = false
performance counter extensions = false
MWAITX/MONITORX supported = false
brand = "AMD Phenom(tm) II X4 965 Processor"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x10 (16)
instruction associativity = 0xff (255)
data # entries = 0x30 (48)
data associativity = 0xff (255)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x20 (32)
instruction associativity = 0xff (255)
data # entries = 0x30 (48)
data associativity = 0xff (255)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (KB) = 0x40 (64)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 0x2 (2)
size (KB) = 0x40 (64)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x80 (128)
data associativity = 2-way (2)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x200 (512)
instruction associativity = 4-way (4)
data # entries = 0x200 (512)
data associativity = 4-way (4)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 16-way (8)
size (KB) = 0x200 (512)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x40 (64)
lines per tag = 0x1 (1)
associativity = 48-way (11)
size (in 512KB units) = 0xc (12)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = true
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = true
TM: thermal monitor = true
STC: software thermal control = true
100 MHz multiplier control = true
hardware P-State control = true
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x30 (48)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
Logical CPU cores (0x80000008/ecx):
number of CPU cores - 1 = 0x3 (3)
ApicIdCoreIdSize = 0x2 (2)
SVM Secure Virtual Machine (0x8000000a/eax):
SvmRev: SVM revision = 0x1 (1)
SVM Secure Virtual Machine (0x8000000a/edx):
nested paging = true
LBR virtualization = true
SVM lock = true
NRIP save = true
MSR based TSC rate control = false
VMCB clean bits support = false
flush by ASID = false
decode assists = false
SSSE3/SSE5 opcode set disable = false
pause intercept filter = false
pause filter threshold = false
AVIC: AMD virtual interrupt controller = false
virtualized VMLOAD/VMSAVE = false
virtualized GIF = false
NASID: number of address space identifiers = 0x40 (64):
L1 TLB information: 1G pages (0x80000019/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x30 (48)
data associativity = full (15)
L2 TLB information: 1G pages (0x80000019/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x10 (16)
data associativity = 8-way (6)
SVM Secure Virtual Machine (0x8000001a/eax):
128-bit SSE executed full-width = true
MOVU* better than MOVL*/MOVH* = true
256-bit SSE executed full-width = false
Instruction Based Sampling Identifiers (0x8000001b/eax):
IBS feature flags valid = true
IBS fetch sampling = true
IBS execution sampling = true
read write of op counter = true
op counting mode = true
branch target address reporting = false
IbsOpCurCnt and IbsOpMaxCnt extend 7 = false
invalid RIP indication support = false
fused branch micro-op indication support = false
IBS fetch control extended MSR support = false
IBS op data 4 MSR support = false
(instruction supported synth):
CMPXCHG8B = true
conditional move/compare = true
PREFETCH/PREFETCHW = true
(multi-processing synth): multi-core (c=4)
(multi-processing method): AMD
(APIC widths synth): CORE_width=2 SMT_width=0
(APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
(synth) = AMD Phenom II X4 (Deneb RB-C3) [K10], 45nm 965 Processor
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