B>> I guess I am confused. The nand gate in the symbol lib would just
keep its old pinnumbers, which would correspond to whatever
asssignments are in the .sym file, i.e. the pinouts for a DIP-14 or
whatever. The place wehre this is overwritten is in the .sch file.
Perhaps I have missed your point? If so, please elaborate...
Consider a TC7S00F single nand gate. Input on pins 1 and 2, output on
4, gnd on 3, vcc on 5. Now consider a 7400FK quad nand gate. Inputs
on pins 2/6/13/18 and 3/8/14/19, outputs on 4/9/12/16, gnd on 10, vcc
on 20.
OK. But in this case I'd just say: these are two different symbols.
One is a quad nand gate with slotting, and the other is a single
nand.
Making them the same symbol is a whole different issue, introducing
its own set of complexities. I don't think gEDA supports this now,
nor do I think it should support it in the future. It implies that we
need that level of indirection between symbols and footprints which we
previously discussed.
Therefore, assuming that such a case calls for two separate symbols,
my humble scheme would never encounter the situation you propose,
right?
That's easy. It's the job of gnetlist to take that info from the .sch
file and stick it into the netlist. AFAIK, gnetlist (& gsch2pcb)
already writes pinnumber, pinname, and pinlabel into the netlist. Or
am I wrong?
I didn't see a "pinname" attribute in the master list.
Fine. If "pinname" not there, it doesn't get written, right?
The only pin attrib you really need for netlisting to PCB is
pinnumber; everything else is gravy.
Stuart
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