On Thu, 2007-11-08 at 08:59 -0600, John Griessen wrote: > Peter TB Brett wrote: > > On Wednesday 07 November 2007 17:54:19 John Griessen wrote: > > > >> What do you think of adding hierarchic schematics that handle instances of > >> subschematics so they are autonumbered, generate a good flat netlist with > >> long names, and support embedded verilog chunks? > > > > Good idea. Actually, the big problem here is allowing attributes to have > > different values depending on context. > > Are you meaning the context of an instance of a symbol in a drawing, or > turning a reference like 0:4 > into a list of instances like 0,1,2,3,4 where you come across the text inside > a symbol?
I think this is referring to to the need / desire to be able to over-ride the attributes of instantiated circuits. Little things like refdes (still handled just like any other attribute) are best changed once you instantiate a hierarchical circuit. (Depending on your numbering schem). Even if you choose to build a flat name out of a path like "module2/subckt1/R10", (avoiding clashing R10), you might still like to alter other attributes for each sub-circuit. > > This is a non-trivial problem (I've recently been working on datastructures > > & > > algorithms that might allow it to work). > > The biggest problems are: > > > > - the current assumption that each text object has only one possible value > > > > - the lack of a defined "project" concept that would make it easier to > > "look > > up" what the current value to display would be. > > We could benefit multiple ways from making a spec for a project. So we can > use > that info. > > John G > -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
