The message below didn't reach you, so I'll try it this way.
Alan Feldstein
Cosmic Horizon
http://www.alanfeldstein.com/
-------- Original Message --------
Subject: RE: Latch gate patch bugs
From: [EMAIL PROTECTED]
Date: Fri, December 21, 2007 1:07 pm
To: Stephen Williams <[EMAIL PROTECTED]>
Steve,
I'm still working toward this. On the way, I found and fixed a bug that is activated when DEBUG is defined in a MINGW32 environment. When I tried to create a patch just for that, I got:
C:\Feldstein\git\icarus_verilog_cloned>git format-patch origin/v0_8-branch
0001-Fixed-dangling-latch-gate-inputs.patch
0002-Removed-UML-not-for-publication.patch
0003-Restore-UML-for-local-use.patch
0004-Presense-of-UML-would-interfere-will-all-subsequent.patch
0005-Fixed-DEBUG-for-MINGW32.patch
C:\Feldstein\git\icarus_verilog_cloned>
This
seems to indicate that my earlier patch set (starting with
Fixed-dangling-latch-gate-inputs.patch), was not committed to your
repository. That is probably wise, due to the issue you reported below,
but I just want to confirm my understanding.0001-Fixed-dangling-latch-gate-inputs.patch
0002-Removed-UML-not-for-publication.patch
0003-Restore-UML-for-local-use.patch
0004-Presense-of-UML-would-interfere-will-all-subsequent.patch
0005-Fixed-DEBUG-for-MINGW32.patch
C:\Feldstein\git\icarus_verilog_cloned>
If the "dangling" patch has not been committed, then my "mingw32" patch would probably be premature and I'll work on the issue below before sending you a comprehensive patch.
Alan
-------- Original Message --------
Subject: Latch gate patch bugs
From: Stephen Williams <[EMAIL PROTECTED]>
Date: Fri, October 26, 2007 4:13 pm
To: "Alan M. Feldstein" <[EMAIL PROTECTED]>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
I reran the regression tests and I'm finding that there have been
some regressions that seem like they came from your patches. The
following is a diff of the report I expect from the report I'm
getting after your patches. Can you look into these?
% diff regression_report-v0.8.txt regression_report.txt
214c214
< unary_minus4 Ran-PASSED-
- ---
> unary_minus4 Assertion-Compiler Error-
811c811
< pr1489568 Ran-PASSED-
- ---
> pr1489568 Assertion-Compiler Error-
813c813
< pr1491355 Sorry-Unable-Compiler Error-
- ---
> pr1491355 Unable-Compiler Error-
910c910
< pr1746848 Ran-PASSED-
- ---
> pr1746848 Ran-FAILED-
934,935c934,935
< pr1795005a Ran-PASSED-
< pr1795005b Ran-FAILED-
- ---
> pr1795005a Ran-FAILED-
> pr1795005b Ran-PASSED-
941c941
< Tests passed: 777, failed: 178, Unhandled: 9 Unable: 3, Assert: 7,
Parse Errs: 3
- ---
> Tests passed: 774, failed: 181, Unhandled: 8 Unable: 3, Assert: 9, Pa
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