I was wondering what the Verilog LRM has to say about sizing ports in the simulator. I have seen that the latest version of the OVL library uses input ports to functions that are unsized (no range information associated with them), but they are internally declared as integers. Example:
function foo; input a; integer a; begin ... end endfunction What is the rule here? Typically, when signals have no range information, their size is considered to be one bit wide, and I was under the assumption that inputs, outputs and inouts needed to be sized correctly when their port direction is specified; however, it seems that Icarus Verilog will size them to be 32 bits in this case when dumping them to the VCD file (which is probably the right thing to do). Is there some sort of "override" rule being used in this case where the input port is being "resized" to 32 bits because of the integer declaration later on? Any specifics you can share are greatly appreciated. Thanks, Trevor Williams _______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
