Trevor Williams wrote: > I was wondering what the Verilog LRM has to say about sizing ports in > the simulator. I have seen that the latest version of the OVL library > uses input ports to functions that are unsized (no range information > associated with them), but they are internally declared as integers. > Example: > > > function foo; > > input a; > > integer a; > > begin > ... > end > > endfunction
The "integer" declaration of the port implies a width (that width being defined by the compiler.) The "integer" declaration is mostly the same as "reg signed [N-1:0]", where N depends on the compiler and/or compilation run. (N >= 32). The "input a;" looks like it has no width/type specification, but that just means that the type specification comes from elsewhere, in this case the "integer a;". That's true of module ports as well. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." _______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
