Bruce -
On Fri, Apr 11, 2008 at 11:16:45PM +0800, bruce cheng wrote:
> Marked blue should be interpret
Next time please flag things in a way that can be read in text
form. I rarely fire up a web browser just to read mail.
> When I use Iverilog to parse this for loop in testbench
>
> for ( ADDR = 6'b000000 ; ADDR <= 6'b111111 ; ADDR = ADDR + 6'b000001 )
> begin
> #10 ;
> $display ( "%b --> %b %b %b %b %b %b", ADDR,
> SEL5,SEL4,SEL3,SEL2,SEL1,SEL0 ) ;
> End
^^^ typo for end
> as equal or smaller according to
> Verilog IEEE. However, the parser set it as give value to ADDR, then the
> loop can not break.
You don't give quite enough info to verify, but it sure looks
like you hit the classic trap of rolling your unsigned arithmetic
instead of hitting a termination condition. Is your ADDR definition
reg [5:0] ADDR;
?
The git variety of Icarus Verilog, at least, parses your code correctly,
and gives a nice warning:
cheng.v:5: warning: condition expression of for-loop is constant.
because ADDR <= 6'b111111 is true for every six-bit value of ADDR.
If you ignore that, the simulation happily goes into an infinite loop.
Just as an experiment, try changing the termination condition to
ADDR <= 6'b111110
Then you can decide how you want to handle the loop for real.
Maybe declare ADDR as
reg [6:0] ADDR;
?
- Larry
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