Hi,
When I use Iverilog to parse this for loop in testbench
for ( ADDR = 6'b000000 ; ADDR <= 6'b111111 ; ADDR = ADDR + 6'b000001 )
begin
#10 ;
$display ( "%b --> %b %b %b %b %b %b", ADDR,
SEL5,SEL4,SEL3,SEL2,SEL1,SEL0 ) ;
End
Marked blue should be interpret as equal or smaller according to
Verilog IEEE. However, the parser set it as give value to ADDR, then the
loop can not break.
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