>what tools do people use to get some graphical representation of some >verilog implementation? Synplicity Synplify had something like that, but I >don't have the Demo license any longer. The layout of the generated schema >also wasn't very satisfying, something that probably isn't easy to solve...
Everytime I look at a machine generated schematic I know that I still have job security. They have a long way to go. The weird thing is that autogenerating a schematic is very similar to autorouting a PCB. You just have a different rule set. Heres what I would like to be able do: 1) start a schematic tool and read in valid netlist file. 2) have the tool find all the symbols in the netlist and autoplace them on a blank sheet. 3) display the net connections between parts with a rats nest. 4) allow the designer to rearrange the part in a more meaningful pattern. 5) let the tool autoroute the nets into neat looking wires using schematic connection rules. That would go a long way to producing usable schematics. John Eaton
