From: Tom Hawkins <[EMAIL PROTECTED]> Subject: Re: gEDA: FNF: Netlist format for Confluence and Informal Date: Wed, 29 Dec 2004 19:05:48 -0600 Message-ID: <[EMAIL PROTECTED]>
> Karel Kulhavy wrote: > > On Sun, Nov 21, 2004 at 11:40:17PM -0600, Tom Hawkins wrote: > > > >>I started to define the format for FNF: the future netlist format of > >>Confluence and InFormal. > >> > >>FNF is a flat netlist that retains hierarchical scoping. The netlist is > >>a directed graph of primitive RTL operations, called cells. Some basics: > > > > > > What is RTL? > > Register Transfer Level (RTL) is the most common abstraction level for > digital design. Ehum! Register Transfer Logic (RTL). Basically, you have a bunch of registers being clocked by a common clock, and then you have logic inbetween the registers. The main point is to keep things in one synchronous level, and you can make very easy (relatively) timing analysis compared to the more complex situation of going between different clocks or even asynchronous clocks. The RTL abstraction is a very strong concept in that the simplification allows for much less hassle and synthesis becomes much easier. As registers we talk D-flip flops or similar flip-flops. Latches are forbidden since they grossly break the timing properties when being "open". Cheers, Magnus
