Tom Hawkins wrote:
Magnus Danielson wrote:
What is RTL?
Register Transfer Level (RTL) is the most common abstraction level
for digital design.
Ehum! Register Transfer Logic (RTL).
Some say toe-ma-toe some say toe-may-toe. :-)
http://en.wikipedia.org/wiki/Register_transfer_level
Traditionally, RTL sits between behavioral level and gate level. And
now there's a lot of marketing buzz about Transaction Level (TL)
modeling, which is essentially an object-oriented paradigm for hardware
(think of bus transactions as method calls).
The interesting aspect of behavioral and transaction level modeling is
there are now tools on the market to synthesize these higher abstraction
levels. When will gEDA follow, I wonder?
Which are those tools that should be followed? As you say 'now' I
assume you don't mean behaviorial synthesis, as that has been
available for a considerable time (but never became very popular).
Though Confluence is an RTL language, it obtains an abstraction level
higher than Verilog/VHDL do to its functional programming
characteristics (higher-order datatypes, lexical scoping, referential
transparency, etc.).
Perhaps, but if I understand it correctly it does this by abstracting away
features such as event driven semantics and procedural constructs, which
make it only applicable for a very specific kind of applications. For example,
not for systems with multiple clocks. So the comparison may be misleading.
Jan
--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Using Python as a hardware description language:
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