gEDA: 0 length signals in iverilog

[Nikolay V. Pyatkov]

What should be the output of the program below in absolutely correct verilog 
simulator?

Thanks,
Nikolay


`timescale 1 ns / 1 ns

module test_wait (/*AUTOARG*/ ) ;

    reg  a;

    initial begin
        $dumpfile ("test_wait.vcd");
        $dumpvars (0, test_wait.a);
    end
    
    initial begin
      a = 0;
      forever begin
          wait (a == 1);
          $display ("in wait a = 1 at time %t", $time);
          wait (a == 0);
          $display ("in wait a = 0 at time %t", $time);
      end
    end
    
    always @(a)
          $display ("in always a = %d at time %t", a, $time);
      
    initial begin
        #3; a = 1; a = 0;
        #1; a = 1; a = 0;
        #1; a = 1; a = 0;
        #1;
        $finish;
    end
                  
endmodule // test_wait