On Wednesday February 16 2005 09:18 am, Anthony J Bybell wrote: > On Wed, 16 Feb 2005, Nikolay V. Pyatkov wrote: > > What should be the output of the program below in absolutely correct > > verilog simulator? > > > > Thanks, > > Nikolay > > #1; a = 1; #0; a = 0; > > ...to do what you're trying to do, you need to put a zero delay in there > in order to force the event list to be re-evaluated. This is standard > verilog behavior. > > -t
In RTL code I have c = a &b; Some times on the same clock edge a goes hi, b goes low. Which is perfectly fine. In hardware there will be a glitch but it will not be registered on the next clock edge. I behavioral code I had wait (c); Which was triggered by the glitch. My mistake. But in the vcd dump there is no changes on the signal though $display shows them. always @(vi_rdy_i ) $display(...) outputs: vi_rdy_i = 1 at time 56664 vi_rdy_i = 0 at time 56664 I thought, there should be some consistence in vvp behavior and vcd dump. If the transition on the signal can trigger wait() or always @() the vcd trace should show the transition. Nikolay
