On Wed, 2006-09-27 at 09:59, John Luciani wrote:
> On 9/27/06, Vaughn Treude <[EMAIL PROTECTED]> wrote:
> > On Wed, 2006-09-27 at 07:48, John Luciani wrote:
> > > On 9/27/06, Vaughn Treude <[EMAIL PROTECTED]> wrote:
> > >
> > > > I also hadn't yet figured out how to connect Vcc to +5V and Vss to
> > > > ground. Googling I found a reference to using netname for this
> > > > purpose. So I added the netname Vcc to one of the +5V symbols and Vss
> > > > to one of the ground symbols, and yet these aren't hooking up either.
> > > >
> > > > I wonder if there's something else I might be missing.
> > >
> > > You are probably using schematic symbols with embedded power pins that
> > > have
> > > names that differ from your netnames. Use a text editor and look for the
> > > net
> > > attributes in the symbols you are using. If you search the list you
> > > will see various discussions of embedded power pins.
> > >
> >
> > I've opened the different IC symbols and displayed the details. Some
> > use Vcc, others VDD, some VSS, others GND. So I added Vcc and VDD to a
> > +5V symbol and the other two to the ground symbol. Didn't help, sad to
> > say.
>
> You should be able to connect these. Create a *simple* schematic using
> embedded symbols and post it. To get embedded symbols select the
> "Embed component in schematic" option in the "Select component
> window.
>
Does it only work when all the components are embedded? Sounds like
that could make the resulting file pretty big.
I've attached the SCH file rather than putting it in line - hope that's
OK. I've embedded all the components, and it still doesn't consolidate
+5V and Vcc.
I'm using gschem version 20060123. Do any of the versions have known
bugs in this respect?
Vaughn T
> >
> > > It is best to "Just say no!" to embedded power pins ;-)
> > >
> >
> > Sorry, I'm a newbie, I don't know how to do that. If it involves
> > redesigning existing symbols, I don't have time to change them all. If
> > there is another way to do it, I'm open to suggestions.
>
> The script below will create a symbol without embedded power connections
> for each symbol file found in the current working directory. See the script
> for usage information. Backup your files in the CWD just in case.
>
> (* jcl *)
>
> -
> http://www.luciani.org
>
>
> #!/usr/bin/perl
>
> # Copyright (C) 2006 John C. Luciani Jr.
>
> # This program may be distributed or modified under the terms of
> # version 0.2 of the No-Fee Software License published by
> # John C. Luciani Jr.
>
> # A copy of the license is at the end of this file.
>
> #####
>
> # For each symbol in the current directory this script creates a new
> # symbol without the embedded power connections and a new symbol with
> # only the power pins. The symbol without the power pins has an "_np"
> # suffix. The symbol containing only the power pins has a "_pwr"
> # suffix. Since many symbols contain the same pinout for power pins
> # the power pin symbol is a symlink to a generic symbol.
>
> # This script only works for symbols with one power net and one
> # ground. The routine that creates the power pin symbols has
> # specifications for only two pins.
>
> use strict;
> use warnings;
> use Carp;
> use IO::File;
>
> # @Power_pins ... each element of this array is an anonymous hash containing
> # the filename, Vcc pin number, and GND pin number.
> # @Net_names .... names of the power nets to remove.
> # @Files ........ all of the symbol files in the current directory.
>
> my @Net_names = $#ARGV == -1 ? qw(Vcc GND) : @ARGV;
> my @Files = <*.sym>;
> my @Power_pins;
>
> # To find the power pins we look for a text line followed by a
> # net=NET_NAME line where NET_NAME is an element in the array
> # @Net_names
>
> foreach my $filename (@Files) {
>
> # skip the files that were created by this script.
>
> next if $filename =~ /_np.sym$/; # already done
> next if $filename =~ /^pwr/; # generic power symbol
> next if $filename =~ /_pwr.sym$/; # power symbol symlink
> print "$filename\n";
> @ARGV = ($filename);
> my $np_filename = $filename;
> $np_filename =~ s/\.sym/_np.sym/;
> my %pins; # contains the filename and power pins for the current symbol
> open(OUT, ">$np_filename") || croak "Could not open $np_filename
> for output: $!";
> while (<>) {
> print(OUT), next unless /^\s*T/;
>
> # Found a text line.
>
> my $text = $_;
> my $line = <>;
> my $power_net_p;
> foreach my $net_name (@Net_names) {
> next unless $line =~ /^\s*net\s*=\s*$net_name\s*:\s*(\d+)/;
> $pins{$net_name} = $1;
> $power_net_p = 1;
> last;
> }
> print(OUT $text, $line) unless defined $power_net_p;
> }
> close(OUT) || croak "Could not close $np_filename";
> push @Power_pins, { filename => $filename, %pins };
> }
>
> # gschem constants --- DO NOT CHANGE THESE
>
> use constant NORMAL_PIN => 0;
> use constant FIRST_POINT_ACTIVE => 0;
> use constant VISIBLE => 1;
> use constant SHOW_VALUE => 1;
> use constant ANCHOR_SW => 0;
> use constant ANCHOR_NW => 2;
> use constant ANCHOR_N => 5;
> use constant ANCHOR_S => 3;
> use constant ANCHOR_SE => 6;
> use constant ANCHOR_NE => 8;
> use constant TEXT_FORMAT => "T %i %i %i %i %i %i %i %i %i\n%s\n";
>
>
> # Change these constants and values in the %Pin_param
> # hash to change the power symbol appearance.
>
> use constant REFDES_X2_OFFSET => -25;
> use constant REFDES_Y2_OFFSET => 25;
> use constant REFDES_ALIGN => ANCHOR_SE;
> use constant TEXT_COLOR => 5;
> use constant TEXT_SIZE => 6;
> use constant PIN_LENGTH => 100;
> use constant PIN_SPACING => 300;
> use constant PIN_COLOR => 5;
> use constant SYM_OFFSET => 100;
>
> # hash key 0 corresponds to the first power net.
> # hash key 1 corresponds to the second power net
>
> my %Pin_param = (0 => { pin_label_align => ANCHOR_N,
> pin_label_x2_offset => 0,
> pin_label_y2_offset => -25,
> pin_number_align => ANCHOR_SW,
> pin_number_x2_offset => 25,
> pin_number_y2_offset => 25,
> x1 => 0 + SYM_OFFSET,
> y1 => 2 * PIN_LENGTH + PIN_SPACING + SYM_OFFSET,
> x2 => 0 + SYM_OFFSET,
> y2 => PIN_LENGTH + PIN_SPACING + SYM_OFFSET},
> 1 => { pin_label_align => ANCHOR_S,
> pin_label_x2_offset => 0,
> pin_label_y2_offset => 25,
> pin_number_align => ANCHOR_NW,
> pin_number_x2_offset => 25,
> pin_number_y2_offset => -25,
> x1 => 0 + SYM_OFFSET,
> y1 => 0 + SYM_OFFSET,
> x2 => 0 + SYM_OFFSET,
> y2 => PIN_LENGTH + SYM_OFFSET});
>
>
> # Each element in @Power_pins is an anonymous hash containing the
> # power pin nets and the filename they came from.
>
> # $pin_ref is a reference to the hash.
>
> foreach my $pin_ref (@Power_pins) {
>
> # Skip parts that do not have an entry for both parts.
>
> my $missing_pwr_nets_p;
> foreach my $net_name (@Net_names) {
> next if defined $pin_ref->{$net_name};
> printf(" file %s is missing the $net_name net\n",
> $pin_ref->{filename});
> $missing_pwr_nets_p = 1;
> }
> next if $missing_pwr_nets_p;
> my $symbol_name = sprintf("pwr_%s_%i_%s_%i.sym",
> map { $_ => $pin_ref->{$_} } @Net_names);
> if (-e $symbol_name) {
> # Do not overwrite an existing power symbol
> } else {
> my $fh = IO::File->new(">$symbol_name")
> || croak "Could not open $symbol_name for output: $!";
> $fh -> print("v 20031231 1\n");
> foreach my $i (0..1) {
>
> # output the pins
>
> my $net_name = $Net_names[$i];
> &pin(fh => $fh,
> pin_number => $pin_ref->{ $net_name },
> pin_name => $net_name,
> % { $Pin_param{$i} });
> }
>
> # output the refdes
>
> $fh -> printf(TEXT_FORMAT,
> REFDES_X2_OFFSET + $Pin_param{0}{x2},
> REFDES_Y2_OFFSET + $Pin_param{0}{y2},
> TEXT_COLOR,
> TEXT_SIZE,
> VISIBLE,
> SHOW_VALUE,
> 0,
> REFDES_ALIGN,
> 1,
> 'refdes=U?');
>
> $fh -> close() || croak "Could not close $symbol_name: $!";
> }
> my $symlink_name = $pin_ref->{filename};
> $symlink_name =~ s/\.sym$/_pwr.sym/;
> system("rm $symlink_name") if -l $symlink_name;
> system("ln -s $symbol_name $symlink_name");
> }
>
> sub pin {
> my %arg = @_;
> $arg{fh} -> printf("P %i %i %i %i %i %i %i\n",
> $arg{x1}, $arg{y1}, $arg{x2}, $arg{y2},
> PIN_COLOR, NORMAL_PIN, FIRST_POINT_ACTIVE);
> $arg{fh} -> printf("{\n");
> $arg{fh} -> printf(TEXT_FORMAT,
> $arg{pin_label_x2_offset} + $arg{x2},
> $arg{pin_label_y2_offset} + $arg{y2},
> TEXT_COLOR,
> TEXT_SIZE,
> VISIBLE,
> SHOW_VALUE,
> 0,
> $arg{pin_label_align},
> 1,
> "pinlabel=$arg{pin_name}");
> $arg{fh} -> printf(TEXT_FORMAT,
> $arg{pin_number_x2_offset} + $arg{x2},
> $arg{pin_number_y2_offset} + $arg{y2},
> TEXT_COLOR,
> TEXT_SIZE,
> VISIBLE,
> SHOW_VALUE,
> 0,
> $arg{pin_number_align},
> 1,
> "pinnumber=$arg{pin_number}");
> $arg{fh} -> printf("}\n");
> }
>
> # Style (adapted from the Perl Cookbook, First Edition, Recipe 12.4)
>
> # 1. Names of functions and local variables are all lowercase.
> # 2. The program's persistent variables (either file lexicals
> # or package globals) are capitalized.
> # 3. Identifiers with multiple words have each of these
> # separated by an underscore for readability.
> # 4. Constants are all uppercase.
> # 5. If the arrow operator (->) is followed by either a
> # method name or a variable containing a method name then
> # there is a space before and after the operator.
>
>
> ##### No-Fee Software License Version 0.2
>
> #### Intent
>
> ### The intent of this license is to allow for distribution of this
> ### software without fee. Usage of this software other than
> ### distribution, is unrestricted.
>
> #### License
>
> ### Permission is granted to make and distribute verbatim copies of
> ### this software provided that (1) no fee is charged and (2) the
> ### copyright notice and license statement are preserved on all copies.
>
> ### Permission is granted to make and distribute modified versions of
> ### this software provided that the entire resulting derived work is
> ### distributed (1) without fee and (2) with a license identical to
> ### this one.
>
> ### This software is provided by the author "AS IS" and any express or
> ### implied warranties, including, but not limited to, the implied
> ### warranties of merchantability and fitness for a particular purpose
> ### are disclaimed. In no event shall the author be liable for any
> ### direct, indirect, incidental, special, exemplary, or consequential
> ### damages (including, but not limited to, procurement of substitute
> ### goods or services; loss of use, data, or profits; or business
> ### interruption) however caused and on any theory of liability,
> ### whether in contract, strict liability, or tort (including
> ### negligence or otherwise) arising in any way out of the use of this
> ### software, even if advised of the possibility of such damage.
>
>
> _______________________________________________
> geda-user mailing list
> [email protected]
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
>
>
v 20060123 1
C 6600 83500 1 0 0 EMBEDDEDgnd-1.sym
[
P 6700 83600 6700 83800 1 0 1
{
T 6758 83661 5 4 0 1 0 0 1
pinnumber=1
T 6758 83661 5 4 0 0 0 0 1
pinseq=1
T 6758 83661 5 4 0 1 0 0 1
pinlabel=1
T 6758 83661 5 4 0 1 0 0 1
pintype=pwr
}
L 6600 83600 6800 83600 3 0 0 0 -1 -1
L 6655 83550 6745 83550 3 0 0 0 -1 -1
L 6680 83510 6720 83510 3 0 0 0 -1 -1
T 6900 83550 8 10 0 0 0 0 1
net=GND:1
]
{
T 6600 83500 5 10 1 1 0 0 1
netname=GND
}
C 6700 86700 1 0 0 EMBEDDED5V-plus-1.sym
[
P 6900 86700 6900 86900 1 0 0
{
T 6950 86750 5 6 0 1 0 0 1
pinnumber=1
T 6950 86750 5 6 0 0 0 0 1
pinseq=1
T 6950 86750 5 6 0 1 0 0 1
pinlabel=1
T 6950 86750 5 6 0 1 0 0 1
pintype=pwr
}
L 6750 86900 7050 86900 3 0 0 0 -1 -1
T 6775 86950 9 8 1 0 0 0 1
+5V
T 7000 86700 8 8 0 0 0 0 1
net=+5V:1
]
{
T 6700 86700 5 10 1 1 0 0 1
netname=Vcc
}
N 4700 85400 4400 85400 4
N 4400 85400 4400 85200 4
N 4400 85200 6100 85200 4
N 6100 84500 6100 85200 4
N 4800 84700 4500 84700 4
N 4500 84700 4500 85000 4
N 4500 85000 6500 85000 4
N 6500 85000 6500 85600 4
N 6500 85600 6000 85600 4
C 6800 84400 1 0 0 EMBEDDED7400-1.sym
[
L 7100 84600 7100 85200 3 0 0 0 -1 -1
T 7100 84400 9 8 1 0 0 0 1
7400
L 7100 85200 7500 85200 3 0 0 0 -1 -1
T 7300 85300 5 10 0 0 0 0 1
device=7400
T 7300 85500 5 10 0 0 0 0 1
slot=1
T 7300 85700 5 10 0 0 0 0 1
numslots=4
T 7300 85900 5 10 0 0 0 0 1
slotdef=1:1,2,3
T 7300 86100 5 10 0 0 0 0 1
slotdef=2:4,5,6
T 7300 86300 5 10 0 0 0 0 1
slotdef=3:9,10,8
T 7300 86500 5 10 0 0 0 0 1
slotdef=4:12,13,11
L 7100 84600 7500 84600 3 0 0 0 -1 -1
A 7500 84900 300 270 180 3 0 0 0 -1 -1
V 7850 84900 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 7900 84900 8100 84900 1 0 1
{
T 7900 84950 5 8 1 1 0 0 1
pinnumber=6
T 7900 84850 5 8 0 1 0 2 1
pinseq=3
T 7750 84900 9 8 0 1 0 6 1
pinlabel=Y
T 7750 84900 5 8 0 1 0 8 1
pintype=out
}
P 7100 84700 6800 84700 1 0 1
{
T 7000 84750 5 8 1 1 0 6 1
pinnumber=5
T 7000 84650 5 8 0 1 0 8 1
pinseq=2
T 7150 84700 9 8 0 1 0 0 1
pinlabel=B
T 7150 84700 5 8 0 1 0 2 1
pintype=in
}
P 7100 85100 6800 85100 1 0 1
{
T 7000 85150 5 8 1 1 0 6 1
pinnumber=4
T 7000 85050 5 8 0 1 0 8 1
pinseq=1
T 7150 85100 9 8 0 1 0 0 1
pinlabel=A
T 7150 85100 5 8 0 1 0 2 1
pintype=in
}
T 7300 86650 5 10 0 0 0 0 1
footprint=DIP14
T 7300 86850 5 10 0 0 0 0 1
description=4 NAND gates with 2 inputs
T 7300 87250 5 10 0 0 0 0 1
net=Vcc:14
T 7300 87450 5 10 0 0 0 0 1
net=GND:7
T 7300 87050 5 10 0 0 0 0 1
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
]
{
T 7100 85300 5 10 1 1 0 0 1
refdes=U1
T 6800 84400 5 10 0 0 0 0 1
slot=2
}
N 6500 85100 6800 85100 4
C 4800 84000 1 0 0 EMBEDDED7400-1.sym
[
L 5100 84200 5100 84800 3 0 0 0 -1 -1
T 5100 84000 9 8 1 0 0 0 1
7400
L 5100 84800 5500 84800 3 0 0 0 -1 -1
T 5300 84900 5 10 0 0 0 0 1
device=7400
T 5300 85100 5 10 0 0 0 0 1
slot=1
T 5300 85300 5 10 0 0 0 0 1
numslots=4
T 5300 85500 5 10 0 0 0 0 1
slotdef=1:1,2,3
T 5300 85700 5 10 0 0 0 0 1
slotdef=2:4,5,6
T 5300 85900 5 10 0 0 0 0 1
slotdef=3:9,10,8
T 5300 86100 5 10 0 0 0 0 1
slotdef=4:12,13,11
L 5100 84200 5500 84200 3 0 0 0 -1 -1
A 5500 84500 300 270 180 3 0 0 0 -1 -1
V 5850 84500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 5900 84500 6100 84500 1 0 1
{
T 5900 84550 5 8 1 1 0 0 1
pinnumber=6
T 5900 84450 5 8 0 1 0 2 1
pinseq=3
T 5750 84500 9 8 0 1 0 6 1
pinlabel=Y
T 5750 84500 5 8 0 1 0 8 1
pintype=out
}
P 5100 84300 4800 84300 1 0 1
{
T 5000 84350 5 8 1 1 0 6 1
pinnumber=5
T 5000 84250 5 8 0 1 0 8 1
pinseq=2
T 5150 84300 9 8 0 1 0 0 1
pinlabel=B
T 5150 84300 5 8 0 1 0 2 1
pintype=in
}
P 5100 84700 4800 84700 1 0 1
{
T 5000 84750 5 8 1 1 0 6 1
pinnumber=4
T 5000 84650 5 8 0 1 0 8 1
pinseq=1
T 5150 84700 9 8 0 1 0 0 1
pinlabel=A
T 5150 84700 5 8 0 1 0 2 1
pintype=in
}
T 5300 86250 5 10 0 0 0 0 1
footprint=DIP14
T 5300 86450 5 10 0 0 0 0 1
description=4 NAND gates with 2 inputs
T 5300 86850 5 10 0 0 0 0 1
net=Vcc:14
T 5300 87050 5 10 0 0 0 0 1
net=GND:7
T 5300 86650 5 10 0 0 0 0 1
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
]
{
T 5100 84900 5 10 1 1 0 0 1
refdes=U1
T 4800 84000 5 10 0 0 0 0 1
slot=2
}
C 4700 85100 1 0 0 EMBEDDED7400-1.sym
[
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T 5000 85100 9 8 1 0 0 0 1
7400
L 5000 85900 5400 85900 3 0 0 0 -1 -1
T 5200 86000 5 10 0 0 0 0 1
device=7400
T 5200 86200 5 10 0 0 0 0 1
slot=1
T 5200 86400 5 10 0 0 0 0 1
numslots=4
T 5200 86600 5 10 0 0 0 0 1
slotdef=1:1,2,3
T 5200 86800 5 10 0 0 0 0 1
slotdef=2:4,5,6
T 5200 87000 5 10 0 0 0 0 1
slotdef=3:9,10,8
T 5200 87200 5 10 0 0 0 0 1
slotdef=4:12,13,11
L 5000 85300 5400 85300 3 0 0 0 -1 -1
A 5400 85600 300 270 180 3 0 0 0 -1 -1
V 5750 85600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 5800 85600 6000 85600 1 0 1
{
T 5800 85650 5 8 1 1 0 0 1
pinnumber=3
T 5800 85550 5 8 0 1 0 2 1
pinseq=3
T 5650 85600 9 8 0 1 0 6 1
pinlabel=Y
T 5650 85600 5 8 0 1 0 8 1
pintype=out
}
P 5000 85400 4700 85400 1 0 1
{
T 4900 85450 5 8 1 1 0 6 1
pinnumber=2
T 4900 85350 5 8 0 1 0 8 1
pinseq=2
T 5050 85400 9 8 0 1 0 0 1
pinlabel=B
T 5050 85400 5 8 0 1 0 2 1
pintype=in
}
P 5000 85800 4700 85800 1 0 1
{
T 4900 85850 5 8 1 1 0 6 1
pinnumber=1
T 4900 85750 5 8 0 1 0 8 1
pinseq=1
T 5050 85800 9 8 0 1 0 0 1
pinlabel=A
T 5050 85800 5 8 0 1 0 2 1
pintype=in
}
T 5200 87350 5 10 0 0 0 0 1
footprint=DIP14
T 5200 87550 5 10 0 0 0 0 1
description=4 NAND gates with 2 inputs
T 5200 87950 5 10 0 0 0 0 1
net=Vcc:14
T 5200 88150 5 10 0 0 0 0 1
net=GND:7
T 5200 87750 5 10 0 0 0 0 1
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
]
{
T 5000 86000 5 10 1 1 0 0 1
refdes=U1
T 4700 85100 5 10 0 0 0 0 1
slot=1
}
C 6600 84700 1 270 0 EMBEDDEDresistor-1.sym
[
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L 6600 84200 6800 84300 3 0 0 0 -1 -1
L 6800 84300 6600 84400 3 0 0 0 -1 -1
L 6600 84400 6800 84500 3 0 0 0 -1 -1
T 7000 84400 5 10 0 0 270 0 1
device=RESISTOR
L 6800 84100 6600 84000 3 0 0 0 -1 -1
L 6600 84000 6700 83950 3 0 0 0 -1 -1
P 6700 83800 6700 83950 1 0 0
{
T 6750 83900 5 8 0 1 270 0 1
pinnumber=2
T 6750 83900 5 8 0 0 270 0 1
pinseq=2
T 6750 83900 5 8 0 1 270 0 1
pinlabel=2
T 6750 83900 5 8 0 1 270 0 1
pintype=pas
}
P 6700 84700 6700 84548 1 0 0
{
T 6750 84600 5 8 0 1 270 0 1
pinnumber=1
T 6750 84600 5 8 0 0 270 0 1
pinseq=1
T 6750 84600 5 8 0 1 270 0 1
pinlabel=1
T 6750 84600 5 8 0 1 270 0 1
pintype=pas
}
L 6800 84499 6700 84550 3 0 0 0 -1 -1
T 6600 84700 8 10 0 1 270 0 1
pins=2
T 6600 84700 8 10 0 1 270 0 1
class=DISCRETE
]
{
T 6900 84500 5 10 1 1 270 0 1
refdes=R2
}
C 6800 86700 1 270 0 EMBEDDEDresistor-1.sym
[
L 7000 86100 6800 86200 3 0 0 0 -1 -1
L 6800 86200 7000 86300 3 0 0 0 -1 -1
L 7000 86300 6800 86400 3 0 0 0 -1 -1
L 6800 86400 7000 86500 3 0 0 0 -1 -1
T 7200 86400 5 10 0 0 270 0 1
device=RESISTOR
L 7000 86100 6800 86000 3 0 0 0 -1 -1
L 6800 86000 6900 85950 3 0 0 0 -1 -1
P 6900 85800 6900 85950 1 0 0
{
T 6950 85900 5 8 0 1 270 0 1
pinnumber=2
T 6950 85900 5 8 0 0 270 0 1
pinseq=2
T 6950 85900 5 8 0 1 270 0 1
pinlabel=2
T 6950 85900 5 8 0 1 270 0 1
pintype=pas
}
P 6900 86700 6900 86548 1 0 0
{
T 6950 86600 5 8 0 1 270 0 1
pinnumber=1
T 6950 86600 5 8 0 0 270 0 1
pinseq=1
T 6950 86600 5 8 0 1 270 0 1
pinlabel=1
T 6950 86600 5 8 0 1 270 0 1
pintype=pas
}
L 7000 86499 6900 86550 3 0 0 0 -1 -1
T 6800 86700 8 10 0 1 270 0 1
pins=2
T 6800 86700 8 10 0 1 270 0 1
class=DISCRETE
]
{
T 7100 86500 5 10 1 1 270 0 1
refdes=R1
}
N 6900 85800 6900 84700 4
N 6800 84700 6700 84700 4
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