On 9/27/06, Vaughn Treude <[EMAIL PROTECTED]> wrote:
On Wed, 2006-09-27 at 09:59, John Luciani wrote:
> On 9/27/06, Vaughn Treude <[EMAIL PROTECTED]> wrote:
> > On Wed, 2006-09-27 at 07:48, John Luciani wrote:
> > > On 9/27/06, Vaughn Treude <[EMAIL PROTECTED]> wrote:
> > >
> > > > I also hadn't yet figured out how to connect Vcc to +5V and Vss to
> > > > ground. Googling I found a reference to using netname for this
> > > > purpose. So I added the netname Vcc to one of the +5V symbols and Vss
> > > > to one of the ground symbols, and yet these aren't hooking up either.
> > > >
> > > > I wonder if there's something else I might be missing.
> > >
> > > You are probably using schematic symbols with embedded power pins that
have
> > > names that differ from your netnames. Use a text editor and look for the
net
> > > attributes in the symbols you are using. If you search the list you
> > > will see various discussions of embedded power pins.
> > >
> >
> > I've opened the different IC symbols and displayed the details. Some
> > use Vcc, others VDD, some VSS, others GND. So I added Vcc and VDD to a
> > +5V symbol and the other two to the ground symbol. Didn't help, sad to
> > say.
>
> You should be able to connect these. Create a *simple* schematic using
> embedded symbols and post it. To get embedded symbols select the
> "Embed component in schematic" option in the "Select component
> window.
>
Does it only work when all the components are embedded? Sounds like
that could make the resulting file pretty big.
No. Embedding components is useful when sending your schematic to someone
else who may not use the library that you are using.
I've attached the SCH file rather than putting it in line - hope that's
OK. I've embedded all the components, and it still doesn't consolidate
+5V and Vcc.
The problem is that you did not connect your power symbols to their
respective components with a net. You have the pin ends against each other.
If you move the power symbols and use net connections the schematic will
netlist and load into PCB.
The schematic below will netlist and load into PCB (provided that you
update the footprint attributes to match footprints on your system).
(* jcl *)
--
http://www.luciani.org
v 20050313 1
C 6600 83300 1 0 0 EMBEDDEDgnd-1.sym
[
P 6700 83400 6700 83600 1 0 1
{
T 6758 83461 5 4 0 1 0 0 1
pinnumber=1
T 6758 83461 5 4 0 0 0 0 1
pinseq=1
T 6758 83461 5 4 0 1 0 0 1
pinlabel=1
T 6758 83461 5 4 0 1 0 0 1
pintype=pwr
}
L 6600 83400 6800 83400 3 0 0 0 -1 -1
L 6655 83350 6745 83350 3 0 0 0 -1 -1
L 6680 83310 6720 83310 3 0 0 0 -1 -1
T 6900 83350 8 10 0 0 0 0 1
net=GND:1
]
{
T 6600 83300 5 10 1 1 0 0 1
netname=GND
}
C 6700 86900 1 0 0 EMBEDDED5V-plus-1.sym
[
P 6900 86900 6900 87100 1 0 0
{
T 6950 86950 5 6 0 1 0 0 1
pinnumber=1
T 6950 86950 5 6 0 0 0 0 1
pinseq=1
T 6950 86950 5 6 0 1 0 0 1
pinlabel=1
T 6950 86950 5 6 0 1 0 0 1
pintype=pwr
}
L 6750 87100 7050 87100 3 0 0 0 -1 -1
T 6775 87150 9 8 1 0 0 0 1
+5V
T 7000 86900 8 8 0 0 0 0 1
net=+5V:1
]
{
T 6700 86900 5 10 1 1 0 0 1
netname=Vcc
}
N 4700 85400 4400 85400 4
N 4400 85400 4400 85200 4
N 4400 85200 6100 85200 4
N 6100 84500 6100 85200 4
N 4800 84700 4500 84700 4
N 4500 84700 4500 85000 4
N 4500 85000 6500 85000 4
N 6500 85000 6500 85600 4
N 6500 85600 6000 85600 4
C 4700 85100 1 0 0 EMBEDDED7400-1.sym
[
L 5000 85300 5000 85900 3 0 0 0 -1 -1
T 5000 85100 9 8 1 0 0 0 1
7400
L 5000 85900 5400 85900 3 0 0 0 -1 -1
T 5200 86000 5 10 0 0 0 0 1
device=7400
T 5200 86200 5 10 0 0 0 0 1
slot=1
T 5200 86400 5 10 0 0 0 0 1
numslots=4
T 5200 86600 5 10 0 0 0 0 1
slotdef=1:1,2,3
T 5200 86800 5 10 0 0 0 0 1
slotdef=2:4,5,6
T 5200 87000 5 10 0 0 0 0 1
slotdef=3:9,10,8
T 5200 87200 5 10 0 0 0 0 1
slotdef=4:12,13,11
L 5000 85300 5400 85300 3 0 0 0 -1 -1
A 5400 85600 300 270 180 3 0 0 0 -1 -1
V 5750 85600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 5800 85600 6000 85600 1 0 1
{
T 5800 85650 5 8 1 1 0 0 1
pinnumber=3
T 5800 85550 5 8 0 1 0 2 1
pinseq=3
T 5650 85600 9 8 0 1 0 6 1
pinlabel=Y
T 5650 85600 5 8 0 1 0 8 1
pintype=out
}
P 5000 85400 4700 85400 1 0 1
{
T 4900 85450 5 8 1 1 0 6 1
pinnumber=2
T 4900 85350 5 8 0 1 0 8 1
pinseq=2
T 5050 85400 9 8 0 1 0 0 1
pinlabel=B
T 5050 85400 5 8 0 1 0 2 1
pintype=in
}
P 5000 85800 4700 85800 1 0 1
{
T 4900 85850 5 8 1 1 0 6 1
pinnumber=1
T 4900 85750 5 8 0 1 0 8 1
pinseq=1
T 5050 85800 9 8 0 1 0 0 1
pinlabel=A
T 5050 85800 5 8 0 1 0 2 1
pintype=in
}
T 5200 87350 5 10 0 0 0 0 1
footprint=DIP14
T 5200 87550 5 10 0 0 0 0 1
description=4 NAND gates with 2 inputs
T 5200 87950 5 10 0 0 0 0 1
net=Vcc:14
T 5200 88150 5 10 0 0 0 0 1
net=GND:7
T 5200 87750 5 10 0 0 0 0 1
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
]
{
T 5000 86000 5 10 1 1 0 0 1
refdes=U1
T 4700 85100 5 10 0 0 0 0 1
slot=1
T 4700 85100 5 10 0 0 0 0 1
footprint=DIP-14-300
}
C 6600 84700 1 270 0 EMBEDDEDresistor-1.sym
[
L 6800 84100 6600 84200 3 0 0 0 -1 -1
L 6600 84200 6800 84300 3 0 0 0 -1 -1
L 6800 84300 6600 84400 3 0 0 0 -1 -1
L 6600 84400 6800 84500 3 0 0 0 -1 -1
T 7000 84400 5 10 0 0 270 0 1
device=RESISTOR
L 6800 84100 6600 84000 3 0 0 0 -1 -1
L 6600 84000 6700 83950 3 0 0 0 -1 -1
P 6700 83800 6700 83950 1 0 0
{
T 6750 83900 5 8 0 1 270 0 1
pinnumber=2
T 6750 83900 5 8 0 0 270 0 1
pinseq=2
T 6750 83900 5 8 0 1 270 0 1
pinlabel=2
T 6750 83900 5 8 0 1 270 0 1
pintype=pas
}
P 6700 84700 6700 84548 1 0 0
{
T 6750 84600 5 8 0 1 270 0 1
pinnumber=1
T 6750 84600 5 8 0 0 270 0 1
pinseq=1
T 6750 84600 5 8 0 1 270 0 1
pinlabel=1
T 6750 84600 5 8 0 1 270 0 1
pintype=pas
}
L 6800 84499 6700 84550 3 0 0 0 -1 -1
T 6600 84700 8 10 0 1 270 0 1
pins=2
T 6600 84700 8 10 0 1 270 0 1
class=DISCRETE
]
{
T 6900 84500 5 10 1 1 270 0 1
refdes=R2
T 6600 84700 5 10 0 0 0 0 1
footprint=0805
}
C 6800 86700 1 270 0 EMBEDDEDresistor-1.sym
[
L 7000 86100 6800 86200 3 0 0 0 -1 -1
L 6800 86200 7000 86300 3 0 0 0 -1 -1
L 7000 86300 6800 86400 3 0 0 0 -1 -1
L 6800 86400 7000 86500 3 0 0 0 -1 -1
T 7200 86400 5 10 0 0 270 0 1
device=RESISTOR
L 7000 86100 6800 86000 3 0 0 0 -1 -1
L 6800 86000 6900 85950 3 0 0 0 -1 -1
P 6900 85800 6900 85950 1 0 0
{
T 6950 85900 5 8 0 1 270 0 1
pinnumber=2
T 6950 85900 5 8 0 0 270 0 1
pinseq=2
T 6950 85900 5 8 0 1 270 0 1
pinlabel=2
T 6950 85900 5 8 0 1 270 0 1
pintype=pas
}
P 6900 86700 6900 86548 1 0 0
{
T 6950 86600 5 8 0 1 270 0 1
pinnumber=1
T 6950 86600 5 8 0 0 270 0 1
pinseq=1
T 6950 86600 5 8 0 1 270 0 1
pinlabel=1
T 6950 86600 5 8 0 1 270 0 1
pintype=pas
}
L 7000 86499 6900 86550 3 0 0 0 -1 -1
T 6800 86700 8 10 0 1 270 0 1
pins=2
T 6800 86700 8 10 0 1 270 0 1
class=DISCRETE
]
{
T 7100 86500 5 10 1 1 270 0 1
refdes=R1
T 6800 86700 5 10 0 0 0 0 1
footprint=0805
}
N 6900 85800 6900 84700 4
N 6900 86900 6900 86700 4
N 6700 83800 6700 83600 4
C 4800 84000 1 0 0 EMBEDDED7400-1.sym
[
L 5100 84200 5100 84800 3 0 0 0 -1 -1
L 5100 84800 5500 84800 3 0 0 0 -1 -1
L 5100 84200 5500 84200 3 0 0 0 -1 -1
A 5500 84500 300 270 180 3 0 0 0 -1 -1
V 5850 84500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 5900 84500 6100 84500 1 0 1
{
T 5900 84550 5 8 1 1 0 0 1
pinnumber=6
T 5900 84450 5 8 0 1 0 2 1
pinseq=3
T 5750 84500 5 8 0 1 0 6 1
pinlabel=Y
T 5750 84500 5 8 0 1 0 8 1
pintype=out
}
P 5100 84300 4800 84300 1 0 1
{
T 5000 84350 5 8 1 1 0 6 1
pinnumber=5
T 5000 84250 5 8 0 1 0 8 1
pinseq=2
T 5150 84300 5 8 0 1 0 0 1
pinlabel=B
T 5150 84300 5 8 0 1 0 2 1
pintype=in
}
P 5100 84700 4800 84700 1 0 1
{
T 5000 84750 5 8 1 1 0 6 1
pinnumber=4
T 5000 84650 5 8 0 1 0 8 1
pinseq=1
T 5150 84700 5 8 0 1 0 0 1
pinlabel=A
T 5150 84700 5 8 0 1 0 2 1
pintype=in
}
T 5100 84000 9 8 1 0 0 0 1
7400
T 5300 84900 5 10 0 0 0 0 1
device=7400
T 5300 85100 5 10 0 0 0 0 1
slot=1
T 5300 85300 5 10 0 0 0 0 1
numslots=4
T 5300 85500 5 10 0 0 0 0 1
slotdef=1:1,2,3
T 5300 85700 5 10 0 0 0 0 1
slotdef=2:4,5,6
T 5300 85900 5 10 0 0 0 0 1
slotdef=3:9,10,8
T 5300 86100 5 10 0 0 0 0 1
slotdef=4:12,13,11
T 5300 86250 5 10 0 0 0 0 1
footprint=DIP14
T 5300 86450 5 10 0 0 0 0 1
description=4 NAND gates with 2 inputs
T 5300 86850 5 10 0 0 0 0 1
net=Vcc:14
T 5300 87050 5 10 0 0 0 0 1
net=GND:7
T 5300 86650 5 10 0 0 0 0 1
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
]
{
T 5100 84900 5 10 1 1 0 0 1
refdes=U1
T 4800 84000 5 10 0 0 0 0 1
slot=2
}
N 6700 84700 7000 84700 4
N 6500 85100 7000 85100 4
C 7000 84400 1 0 0 EMBEDDED7400-1.sym
[
L 7300 84600 7300 85200 3 0 0 0 -1 -1
L 7300 85200 7700 85200 3 0 0 0 -1 -1
L 7300 84600 7700 84600 3 0 0 0 -1 -1
A 7700 84900 300 270 180 3 0 0 0 -1 -1
V 8050 84900 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 8100 84900 8300 84900 1 0 1
{
T 8100 84950 5 8 1 1 0 0 1
pinnumber=8
T 8100 84850 5 8 0 1 0 2 1
pinseq=3
T 7950 84900 5 8 0 1 0 6 1
pinlabel=Y
T 7950 84900 5 8 0 1 0 8 1
pintype=out
}
P 7300 84700 7000 84700 1 0 1
{
T 7200 84750 5 8 1 1 0 6 1
pinnumber=10
T 7200 84650 5 8 0 1 0 8 1
pinseq=2
T 7350 84700 5 8 0 1 0 0 1
pinlabel=B
T 7350 84700 5 8 0 1 0 2 1
pintype=in
}
P 7300 85100 7000 85100 1 0 1
{
T 7200 85150 5 8 1 1 0 6 1
pinnumber=9
T 7200 85050 5 8 0 1 0 8 1
pinseq=1
T 7350 85100 5 8 0 1 0 0 1
pinlabel=A
T 7350 85100 5 8 0 1 0 2 1
pintype=in
}
T 7300 84400 9 8 1 0 0 0 1
7400
T 7500 85300 5 10 0 0 0 0 1
device=7400
T 7500 85500 5 10 0 0 0 0 1
slot=1
T 7500 85700 5 10 0 0 0 0 1
numslots=4
T 7500 85900 5 10 0 0 0 0 1
slotdef=1:1,2,3
T 7500 86100 5 10 0 0 0 0 1
slotdef=2:4,5,6
T 7500 86300 5 10 0 0 0 0 1
slotdef=3:9,10,8
T 7500 86500 5 10 0 0 0 0 1
slotdef=4:12,13,11
T 7500 86650 5 10 0 0 0 0 1
footprint=DIP14
T 7500 86850 5 10 0 0 0 0 1
description=4 NAND gates with 2 inputs
T 7500 87250 5 10 0 0 0 0 1
net=Vcc:14
T 7500 87450 5 10 0 0 0 0 1
net=GND:7
T 7500 87050 5 10 0 0 0 0 1
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
]
{
T 7300 85300 5 10 1 1 0 0 1
refdes=U1
T 7000 84400 5 10 0 0 0 0 1
slot=3
}
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