>>>>> "Peter" == Peter TB Brett <[EMAIL PROTECTED]> writes:
> Hi folks, Slightly off-topic, but I need some suggestions: I'm > currently building an ADC board to go with an existing microprocessor > board I have available. It's going to have eight 100 kHz 12-bit serial > ADCs. > Now, the problem I have is that I want to read from all eight channels > simultaneously and at regular intervals, but I have no control over > how often or regularly the microprocessor will request data. > I've written a snippet of VHDL which I could load into a small CPLD to > turn the serial data into a stream of parallel data, but I need to > have a decent size buffer, and affordable configurable logic devices > don't have any RAM worth speaking of and too few registers to > implement a memory controller + buffer manager. Hi, I'm not very experienced with that stuff... but why not just use an async FiFo, like this: http://www.idt.com/?catID=58613 Not very cheap, though. You might even be able to remove the CPLD from the design? Just connect the ADCs' serial output to different bits of the Fifo and clock them all in parallel, with the same clock that clocks data into the FiFo... Then it would be your main uC's task to read the other end of the FiFo and de-interlace the ADCs' data. If the FiFo is big enough, your uC will be able to get that done even if not real-time capable. regards, David -- GnuPG public key: http://user.cs.tu-berlin.de/~dvdkhlng/dk.gpg Fingerprint: B17A DC95 D293 657B 4205 D016 7DEF 5323 C174 7D40 _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
