Hi. I'm new to this group and 'world' of HDL. I worked with Altera's QUARTUS - designing some simple applications in AHDL and VHDL (really, on a basic level). That's when I saw the power of FSM in designing 'simple' logic circuits, and power of VHDL in designing complex logic circuits. Since one area of interest to me is 'programmable logic controllers', I taught that HDL (especially VHDL) could be used in designing PLC 'circuits'. So, I google'd a little and found something called Verilog :) I've downloaded Icarus Verilog and started experimenting.
So, here is what I am trying to do and just don't know how! :) I want to write a verilog 'program', compile it, synthesize it and as a result get a netlist file (or what ever) that lists basic and sequential logic circuits with a description of connections between them. (I hope i've explained it right :) Basically, I want to describe how something works and get schematics with basic logic and sequential circuits. Can I do that with IVerilog? Best regards, Predrag _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
