Predrag Bradaric wrote: > So, here is what I am trying to do and just don't know how! :) > I want to write a verilog 'program', compile it, synthesize it and as > a result get a netlist file (or what ever) that lists basic and > sequential logic > circuits with a description of connections between them. (I hope i've > explained it right :) > Basically, I want to describe how something works and get schematics > with basic logic and sequential circuits. > Can I do that with IVerilog?
For starters, go here: <http://iverilog.wikia.com> The introduction in particular gives to a summary of where Verilog sits in the design process. For your specific case, you are going to use two Verilog tools: a simulator (which can be Icarus Verilog) and a synthesizer (which your Quartus download includes). Your day-to-day design is done with a simulator, and once your simulations run to your satisfaction, to pass your code to the synthesizer to get "gates" for your FPGA. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
