How about a picture from the past? This was a 900 pin fpga where I used via in pad.
http://www.alchemyresearch.com/bga.jpg Steve Meier On Sat, 2007-07-14 at 10:41 -0700, Ben Jackson wrote: > On Sat, Jul 14, 2007 at 08:19:34AM -0700, Steve Meier wrote: > > > > p.s. my current project uses 1020 pin fpgas and was layed out on 12 > > layers. One key is to be willing to swap io pins at layout time to > > minimize the need for traces to cross each other. > > It would be great if someone doing advanced work could post some examples > somewhere. It would give new users confidence that PCB can handle these > things. Darrell Harmon's SBC (4 layer CPU board) was one of the things > that got me to try geda/pcb. > > As for FPGA routing, I also just did an FPGA board, only QFP208 (don't > laugh ;-) and what I did was leave all the FPGA IO pins unassigned, but > named all the nets coming out of the peripherals. Then after I did the > physical layout, I routed the pins as needed, using 'n' to pop up the > rename dialog and see what kind of pins were in the target area (I'm > seriously considering adding the pin name/number under the crosshair to > the status bar!). After routing, optimizing the ratsnest complains that > 'Warning! Net "A13" is shorted to U1 pin 123'. That list guided me in > naming nets connected to the FPGA symbol. Once I was done I just made > a new netlist and verified that the routing was complete. > > I'm considering how to automate the second part. If I pre-drew unnamed > nets hanging off the fpga pins, I could automatically add the netname > attributes based on a PCB-generated report. > _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
