Harold, Can you check that again. 45 mills is 1.143 mm.
Thanks, Steve Meier On Sat, 2007-07-14 at 15:43 -0500, Harold D. Skank wrote: > Steve, > > You're pretty much right about every thing except the pin density. > We're using Vertex 5, with pins spaced at 0.5 mm, pin to pin. This > limits the routing out from each pin to essentially 1 trace between > pins. > > Harold > > On Sat, 2007-07-14 at 08:19 -0700, Steve Meier wrote: > > I think it is the use of the autorouter then that is driving your need > > for layers. > > > > 1700 pins is what an array of 42 by 42 with a 1 millimeter spacing? You > > should be able to get two traces per layer in between each pair of balls. > > > > How many IO lines are you using? xilinx vertext 3 with 1760 pads has > > 1200 io pins which are grouped at the edge of the device. So they penetrate > > > > I agree you need at least one ground layer and 4 power layers. > > > > To get the traces out from under the bga you will need 5 or 6 layers. > > assuming 300 io pins per side clustered near the edges this implies > > around 10 rows of io pins. > > > > I think that this type of device can be done in as few as 12 layers > > (probably pain staking layout) and in say 16 layers comfortably. > > > > Have fun, > > > > Steve Meier > > > > p.s. my current project uses 1020 pin fpgas and was layed out on 12 > > layers. One key is to be willing to swap io pins at layout time to > > minimize the need for traces to cross each other. > > > > Harold D. Skank wrote: > > > Mr. Jackson, > > > > > > I VERY MUCH appreciate your response and comments. In answer to your > > > question, "yes, I will use a 24-layer PCB if it's fully necessary." > > > This issue arises because the principal chip in the circuit has > > > something like 1700 pins and uses 3 to 4 different voltages on something > > > like a 45 mil pin spacing. Without blind/buried vias the high number of > > > layers become necessary to provide the necessary routing space to get > > > connections away from the pins. I will reduce the number of layers to > > > the minimum necessary to achieve a full route. > > > > > > As a matter of record, the greatest number of layers I have had to use > > > in the past was 13. However, the router I was using was more > > > sophisticated (and VERY much more expensive). > > > So, 24 layers are a bit intimidating. > > > > > > Harold Skank > > > > > > On Fri, 2007-07-13 at 19:55 -0700, Ben Jackson wrote: > > > > > >> On Fri, Jul 13, 2007 at 07:40:12PM -0500, Harold D. Skank wrote: > > >> > > >>> I'm on a critical job, pretty large, sufficient that I had to recompile > > >>> for 24 route layers. Following the re-compile, I seem to be OK for > > >>> everything until I attempt to start a route, at which point I get the > > >>> "stale ratsnest" message. > > >>> > > >> Are you really going to use the results of a 24 layer PCB autoroute? > > >> Just > > >> curious. > > >> > > >> Anyway, I modified PCB to highlight the rat that causes the problem. It > > >> seems that it's confused by ratlines that go from a pad to the corner of > > >> the nearest compatible polygon. > > >> > > >> I went into the netlist window and disabled GND and P* (appear to be your > > >> power nets) for rats, remade the netlist and then ran an autoroute. It's > > >> burning up CPU routing the signals now. > > >> > > >> If you are willing to do the power nets by hand, that might be a solution > > >> for you. Otherwise maybe the description above will tip off another > > >> developer as to how to fix the problem. > > >> > > >> > > > > > > > > > > > > _______________________________________________ > > > geda-user mailing list > > > [email protected] > > > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > > > > > > > > > > > > > > _______________________________________________ > > geda-user mailing list > > [email protected] > > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > > > > _______________________________________________ > geda-user mailing list > [email protected] > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
