> > Message: 2 > Date: Tue, 14 Aug 2007 17:14:01 +0930 > From: Ken Sarkies <[EMAIL PROTECTED]> > Subject: Re: gEDA-user: Basic questions from a gEDA & Linux noob > To: gEDA user mailing list <geda-user@moria.seul.org> > Message-ID: <[EMAIL PROTECTED]> > Content-Type: text/plain; charset=ISO-8859-1; format=flowed > > > Felix Fujishiro wrote: > > On Mon, 13 Aug 2007 07:43:42PM -0700, Ben Jackson wrote: > > > > >On Mon, Aug 13, 2007 at 07:33:40PM -0700, Felix Fujishiro wrote: > > >> > > >> I tried to do this by adding the 'net=GND:4' attribute, and that > > works, but > > >> only if pin #4 is visible. > > > > > >I'm not sure what you mean. My Altera FLEX board used a chip-shaped > > >symbol with all the power and gnd hidden using net= attributes. There > > >are no pins for those anywhere. > > > > I guess I'm not being clear.... I'm using gschem for custom digital IC > > design, perhaps there's a difference in the way the tool treats MOS > > components and PCB components? If I remove pin #4 (the substrate/well > > connection) from the MOS symbol, gnetlist spits out a three-terminal > > device instead of a four-terminal device (which I want). > > Perhaps you are deleting the pin? Do you mean to simply hide it on the > schematic? > > Ken
Yes Ken, you are right... I was deleting the pin and that wasn't the answer. I want to hide it on the schematic (and make sure nothing else can connect to it). Message: 5 > Date: Tue, 14 Aug 2007 08:17:36 -0500 > From: John Griessen <[EMAIL PROTECTED]> > Subject: Re: gEDA-user: Basic questions from a gEDA & Linux noob > To: gEDA user mailing list <geda-user@moria.seul.org> > Message-ID: <[EMAIL PROTECTED]> > Content-Type: text/plain; charset=ISO-8859-1; format=flowed > > Felix Fujishiro wrote: > . I'm using gschem for custom digital IC > > design, perhaps there's a difference in the way the tool treats MOS > > components and PCB components? If I remove pin #4 (the substrate/well > > connection) from the MOS symbol, gnetlist spits out a three-terminal > device > > instead of a four-terminal device (which I want). > > Try using four pins and the net= attribute. Then move the pin to be > inboard of the symbol outline and/or turn off visibility... > I was not aware of the difference in netlist output...this workaround > might fix that. > > John Griessen > Ecosensory > > PS Please tell us about your design flow with gEDA for making > chips. What fab? > Which layout tool? Magic? > > John: Yes, as an interim fix, I wound up using a four-pin device with the net=attribute, and then moved the connection end of the 'hard-wired' pin to an off-grid point (to reduce the chance of an accidental connection to another net). But I would like to turn off the visibility, to make it look 'cleaner' and to avoid any chance of a random connection.... could you tell me how I might do that? Regarding our design flow, we're using LayoutEditor for basic cells, though we may move to another one (possibly commercial) for the top level. I originally wanted to use Magic, but ran into some difficulties with it crashing in my tests (segmentation faults, if I remember correctly), and being short on time, didn't want to devote too much time to write a comprehensive tech file if I couldn't guarantee that we wouldn't lose any work should Magic crash. I do like Magic, it has many of the features we need, just needed tool stability more. I can't go into specifics about the foundry right now other than to say it's one of the ones on the leading edge and that it's offshore. Best regards to you both! Felix
_______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
