Dan McMahill wrote: > John Doty wrote: I see very little burden to making that connection explicit. >> And sometimes you may want to connect the N well to something other >> than Vdd.
When I've done layout I always used a layout vs. schem checker that connected the well to its surroundings by layers overlapping, and then a mistake of connecting the required well ties is caught as a short so you couldn't get past that point without having it consistent with your netlist. Having internal connections with a symbol will give a good netlist that is self consistent without the chance of leaving off a substrate connection as you place standard cell symbols on your schematic. If you make a driver out of many standard size transistors and Vss symbols next to each, and accidentally leave off some, you would find a mismatch way late when you do a layout vs. schematic check. Or worse, you could find that running simulations you extended some widths to get size right and find later that the simulation said you needed so many because a row was left with substrate unconnected so far, and the model simulated differently for lack of capacitance to substrate... Any method could have mistakes and wasted time, so create one to match brain-preference-ability of the one using it is best. John Griessen -- Ecosensory Austin TX tinyOS devel on: ubuntu Linux; tinyOS v2.0.2; telosb ecosens1 _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
