On Jan 21, 2008, at 10:43 AM, John Griessen wrote: > John Doty wrote: > >>> - clean schematics are needed for LVS, >> >> What's LVS? Please don't assume we know your jargon. >> > Layout Versus Schematic checker. EDA jargon. Chip design jargon. > Our jargon. >
The people I work with call it "postlayout verification", and the schematic isn't directly involved: we do it at the netlist level. I don't see how you'd do it at the schematic level: the extracted netlists from the layout correspond to schematics that are humanly incomprehensible! But again, I am very far from the VLSI "mainstream". John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ [EMAIL PROTECTED] _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
