John Doty wrote: >> LVS is one of _layout_ verification methods. Others are DRC (often >> separated into several checks: antenna, density etc), ERC, LVL (GDS >> compare). > > I don't know what open source tools exist here. It would be > interesting to investigate incorporating them into a gEDA flow.
There is a netlist vs netlist compare tool that I started to look at. netcmp maybe? It might have been part of magic. It is probably in the archives for this list. Such a netlist vs netlist tool could actually be pretty darn useful in doing forward/backward annotation between a board layout and schematic. My vague memory is that the open source netlist compare tools either weren't open source or that they had some real limitations, but my memory of this is vague at best. -Dan _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
