On Fri, Apr 25, 2008 at 1:18 PM, Ian Chapman <[EMAIL PROTECTED]> wrote: > In my # release: pcb 20080202 version I have:- > DRC[2000 1000 2000 1000 1500 1000] and since they are in square brackets > that works out to be 0.020" spacing and that's fine for through hole but not > so good for TQFP with 0.5mm pad spacing. I'll change the PCB file to 5 or > 10 mil if there is not a GUI for that, what clearance do you use?
I use 7.49/8/8 for design rules. The more important question is what design rules does your process support? Most of the low-cost board houses can do 8/8/8 (* jcl *) -- http://www.luciani.org _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
