On Wed, 2008-04-30 at 14:37 +0100, Peter TB Brett wrote: > On Wednesday 30 April 2008 14:20:37 James Moody wrote: > > My circuit design spans 2 sheets. To carry the signal from one to the > > other I used the output and input flags, and added the attribute > > "netname=CH A_1" to the output on one page and the corresponding input > > on the other page. I did the same with "CH A_2", "CH B_1" and "CH B_2". > > In the resulting netlist these nodes are unnamed, and the connection > > between sheets was not made. I tried again after removing the space in > > the value; no difference. > > > > Netname attributes should be attached to the net segments themselves. At the > moment, the input/output flags are only used for heirachy.
A "net=net_name:1" attached to the input / output connectors works, and is what I often use. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
