On Sat, Oct 25, 2008 at 05:45:20PM -0400, DJ Delorie wrote: > Check your "shrink" size. In your case, it's set to 10 mil, which > means any two touching copper segments must overlap by at least 10 > mil. You have some segments that only overlap by 3 mil.
I didn't look at your file, but I did file a bug against PCB some time ago about the DRC's shrink test misunderstanding cases where two pins or pads overlap. I was hanging power/gnd vias on the edge of SMT cap pads and PCB would think they didn't connect well enough unless I added a trace. Even if the trace was much skinnier than the actual "neck" where the parts overlap. -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
