Hello Peter, I will send the file to you shortly. I found out some strange differences in netlist and pcb libraries generation between my stationary PC and notebook. Both machines have the same system and software versions, I need to fix it up before testing to not make false assumptions. Sorry for delay.
Best Regards, Michael W. > If you have an example which you are able to send me, I'm collecting > test-cases for slow PCB behaviour. I can't promise that I'll be able to > fix it, but I can at least see if I can reproduce the issue, with / > without the no-holes polygon cache. I'd also run it though the OpenGL > HID I've been working on, to see how that compares. > > > -- > Peter Clifton > > Electrical Engineering Division, > Engineering Department, > University of Cambridge, > 9, JJ Thomson Avenue, > Cambridge > CB3 0FA > > Tel: +44 (0)7729 980173 - (No signal in the lab!) > > > > _______________________________________________ > geda-user mailing list > [email protected] > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
