On Wed, 2008-11-19 at 06:04 -0800, Steve Meier wrote: > Peter, > > I believe that gnetlist takes in a hierarchical series of schematics and > flattens the schematics into a flat netlist that may then be exported > into a number of flat formats. In other words the net has been flattened > before reaching the backend. Hierarchical information is retained in > reference designators and in net names.
You are, of course, correct. IIRC, there were a few workarounds for the VHDL / spice backends, where individual pieces were netlisted separately. Its been a while since I looked, and certainly those cases are non-optimal, even if it is possible to retain hierarchy. What I should have said.. Hierarchical input is accepted by gnetlist. Gnetlist's output is always flattened. There are possibly some workarounds available, such as net-listing individual pieces separately, but we (gEDA) really ought to work on doing better. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
