On Thu, Nov 20, 2008 at 1:09 AM, John Doty <[EMAIL PROTECTED]> wrote: > >> Agreed. I didn't mean gnetlist doesn't work with hierarchical designs >> at all - it just didn't produce any useful results last time I tried >> it. > > You haven't clearly stated what your problem was. I've done both > hierarchical VLSI designs (SPICE style: generate a hierarchical > netlist with a Makefile and let the downstream tools flatten it), and > circuit boards (use source= and let gnetlist do the flattening). > Works great for me. Nobody can fix a problem you can't clearly > articulate.
Can you explain in detail how do you generate the hierarchical netlist? Although using Makefile doesn't seem particularly appealing to me (I keep all my design data in a single place - schematics) it could potentially make the flow working until the "proper" netlister is done. >> I've looked into the scheme code but I couldn't find any obvious >> errors. This single error broke my workflow, I think it is important >> enough to inform others that they should not rely on this particular >> feature. > > What error? We discussed several issues here: http://archives.seul.org/geda/user/Jan-2008/msg00249.html Please accept my appologies if those have already been fixed - I haven't used gnetlist since that time. Regards, -r. _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
