Árpád Magosányi wrote: > 2009/1/5 DJ Delorie <[email protected]>: >> If a standard is not documented with freely available documentation, >> it's unlikely any of us will even be interested in it. > > Icarus verilog outputs EDIF for fpga targets... > Of course I would be able to RTFS to figure out the subset it generates, > but in such cases I prefer to implement the standard, not an > interpretation of it.
EDIF still exists? Ouch. EDIF == Every Disk Is Full. EDIF is grammatically an incredibly verbose file format, and lexically inefficient as well. It is also pretty nasty to parse -- very unfriendly for LALR parsing like flex/bison can do for you. Are you trying to read it or write it for your application? From your post, I'm guessing that you want to read it and translate it into something to feed an FPGA synthesis tool. EDIF is a huge standard, and most likely only a tiny subset is used for FPGA descriptions. I suspect that your best option (other than finding a non-EDIF interface for your tool chain) is to try to figure out the subset that you need and just do that. Doing EDIF in its entirety is a huge effort. In fact, I think most vendors that ever supported EDIF only supported subsets of the language. I actually bought (or actually my employer did) a copy of the standard maybe twenty or so years ago. I'm pretty sure I threw it out, but it might still be in the garage, serving as nest material for the mice. If so, the mice are getting more joy from it than I ever did. -dave _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
