On Mon, Jan 5, 2009 at 9:55 PM, Dave N6NZ <[email protected]> wrote: > > EDIF still exists? Ouch. > > EDIF == Every Disk Is Full. > > EDIF is grammatically an incredibly verbose file format, and lexically > inefficient as well. It is also pretty nasty to parse -- very > unfriendly for LALR parsing like flex/bison can do for you.
EDIF failed to meet its goal of a universal EDA exchange format but it wasn't caused by its weaknesses. It was the whole idea of "one format fits all" that failed. EDA packages use completely different abstractions for multiple basic constructs (not to say about more advanced ones) and the effect is that EDIF can only be treated as a lowest common denominator import/export format (and "lowest" means *really* low here). Even though it's not terribly useful there are currently no other formats for exchanging e.g. schematics. Sure, there is OpenAccess but it's more an API than a format and it still imposes some design decisions just like EDIF did. EDIF is fairly widely adopted as a *netlist* exchange format (although structural verilog is more popular now). It's easy to parse (BTW, using bison here would be an overkill) and is as compact as any other text netlist format can be (or better, if compared to VHDL). For a synthesis tool, it currenlty makes more sense to input/output data in verilog. Its structural subset is not much more complicated than EDIF and at very least can be directly simulated (especially if assisted with SDF). Several years ago verilog was not very well supported by some FPGA backend tools but that might have changed by now. Regards, -r _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
