DJ Delorie wrote: > I'm getting close to a final design for my SDRAM board, but I'm > thinking about termination for the SDRAM signals. This board is > faster than anything else I've done before (133MHz 3.3v). > > Updated images here: http://www.delorie.com/electronics/sdram/ > > The left half of the board (U2 left, U1) runs at 24 MHz, no problem. > > The right half of U2, and U2, run at 133MHz. The longest trace is the > CLK line, at just over 3 inches, the shortest is just under an inch. > However, most of those lines are brought out to logic analyzer > connectors, which may add up to another 1.8 inches (DQ11, for example, > has a combined length of 3.9 inches). > > I'm thinking I have enough space to put in some series terminator > packs (8x 0402 SMT) but where and how big? Is it relative to which > chip is driving the trace? Should the logic analyzer go on the fast > side or the slow side, or does it matter? (it's a 500Ms/s analyzer) > > > _______________________________________________ > geda-user mailing list > [email protected] > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user >
That Spartan is capable of sub-nanosecond edges which will far exceed the frequency of your clock. Xilinx will allow you to adjust the slew-rate within limits. Use the built-in terminator resistors on the clock-out pins, not the data lines. If you are so inclined, terminate the clock at the end of line (not at the FPGA source, and past the end of line) with an R-C style, where R = 51-Ohm and C=100 pF. That setup will get you source termination at the FPGA plus end termination with the RC. Terminating data lines is always difficult because they're bidirectional. I suppose you could end-terminate them on both sides, but am sure if it buys you anything, timing wise. Those mictor connectors are a great option, like Ben pointed out. Are you willing to put some buffers at the end of your bus? You know, between the bus and the LA? At least you can minimize the stubs that way. You really don't want to destroy your timing budget due to stubs and the signal integrity headache that comes along for the ride. You could depopulate the buffer in production - or what if the buffer is part of another board, that has the LA connector on it? Just a thought. _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
