DJ Delorie wrote: > I want to simulate the propogation delay through the fpga IOBs and the > traces on the board. However, some of the lines are bidirectional > (specifically, the data lines). It's easy enough (I'm assuming) to > assign a delay on a unidirectional line, but what about bidirectional > lines?
If you want to model the full behavior of the FPGA logic programmed in, without all the details of logic to do that, you would make an assignment conditional on the state of the machine as a bit of procedural code like a case statement embedded in the ordinary verilog that acts all in parallel to model wires and gates... If you want to model enough to synthesize gates, you would specify logic in verilog that has registers and holds states, and the state that switches the bidir port to one or the other way would cause the the wire and register switching delays to be assigned as a verilog combination function of the inputs. The first way is what they call a behavioral model, and second is register transfer level model (RTL). John - _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
