----- Original Message ----- From: DJ Delorie Date: Wednesday, April 22, 2009 12:43 am Subject: gEDA-user: bidirectional delay in verilog? To: [email protected]
> > I want to simulate the propogation delay through the fpga IOBs > and the > traces on the board. However, some of the lines are bidirectional > (specifically, the data lines). It's easy enough (I'm assuming) to > assign a delay on a unidirectional line, but what about bidirectional > lines? > > Are you modeling the FPGA and the DRAM (I'm assuming it's the DRAM, not that it matters so much)? Are you using a test bench to run this? You could do something like this: | FPGA | --------- | DRAM | Make the DRAM a purely functional model, very simple, and add the flight time into to the input and output delays. You can model the DRAM IO as a dedicated input plus a wire- or'd tristate output device. So maybe the flight time on the wire is 1 nS, you setup the DRAM input delay as 1 nS. Then add 1 nS onto the output buffer of the DRAM to model the flight time back to the FPGA. Use a test bench to combine the FPGA and the DRAM into one device, wired together as needed. Then just excercise it anyway you like. It doesn't have to be a test bench per- se, since a hierarchical verilog source file is the same thing, and you can simulate that as well. As for the IOB's. Hmm. One way is to use the timing simulation file that XST creates, post layout. I think it is in verilog, or can be made in verilog via some selection. You can just plug it into the setup I was just mentioning. If that is not the case, then you can model the IOB as a dedicated input and tri-stated output and add the delays you like. (this is how the fpga builds bidirectional lines anyway, they can't build wire-or inside the part) FPGA IOB the wire DRAM IOB |Tri-state output |->>----------------------- >>-| input buffer| |Input Buffer |-<<-| <<-| Tristate output | _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
