Anthony Shanks wrote: > > Haha yeah, except I'm not sure what he says is accurate and I'm not > sure what the resistance is against a hierarchical netlister (without > workarounds like makefiles and such). Every single industry level > netlister I have ever seen does this and I have worked with plenty as > a student and now an engineer in the industry. As someone who manually > looks at netlists on a daily basis, flat netlists are very hard to > read and simulate slow in spice simulators. I'm not even sure a > makefile solution would really work anyway since flat netlisting each > cell separately in a makefile (which I assume John was talking about) > would not be able to automatically produce the subckt statements need > inside the main spice file. Correct me if I am wrong. >
All greek to me. I can totally appreciate the power of Spice et al., but the last time I used that kind of simulation was, oh, waayyy too many years ago and I authored the input files with vi--- they would easily have fit on a page. Yea, I use gaf today to capture schematics and lay out boards--- but that's just scratching the surface of what I can do. I'm still only skin-deep, too ignorant to have even a worthless opinion on the topic. :) b.g. -- Bill Gatliff [email protected] _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
