What verion of Icarus Verilog are you using? Icarus Verilog doesn't support specify blocks before the 0.9 release. I think with the 0.9 release, it is default turned off, you enable it with -gspecify.
Philipp Klaus Krause wrote: > I want to model gate delays, but everything happens without delay. > Icarus gives no errors messages or warnings. I used gates such as the > following: > > module and2 (A, B, O); > input A ; > input B ; > output O ; > > and (O, A, B); > > specify > // delay parameters > specparam > rise = 3.62329:3.62329:3.62329, > fall = 4.98817:4.98817:4.98817; > > // path delays > (A *> O) = (rise, fall); > (B *> O) = (rise, fall); > > endspecify > > endmodule > > Philipp > > > _______________________________________________ > geda-user mailing list > [email protected] > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
