Tamas Szabo wrote: Since all part of the antenna > lines consist of pads, it seems to be a short circuit between the > terminals
I looked at your footprint and it has three terminals and a keep out zone in silkscreen. It's a shame to toss it out -- you could just ignore the DRC errors, placing it last and expecting the error it generates and accepting that for now. We need a way to deal with that behavior in pcb for antennas. Who likes my idea of assigning all same terminal numbers when using antennas? I think that is a reasonable method, since you always are considering an antenna as "custom analog" that you check closely. Putting a printed wiring antenna in wrong way around is chances like "slim and none". Will any ability to treat layout zones as a component naturally come along with the layer and via stack changes in pcb slated for the Linux Fund upgrades? John Griessen -- Ecosensory Austin TX _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
