> Thanks. The chip design tools don't worry with making busses look > any different unless added by the user just for looks. For them, > the different label does it all. But they done' have that > additional constraint of a package.
Right, with verilog "signal" is more abstract - one signal can be a single wire, another signal can be a 48-bit numeric value. In pcb layout, we have to stick with what the laws of physics allow, which means multi-physical-connection "things" have to be explicit and distinct. > I guess bus pin is workable terminology. Bus port for a name > might cause less head aching. I called it "bus pin" meaning a pin that connects to a bus, vs a pin that connects to a net, in gschem. I mean, we already have two fundamental connection types in gschem - nets and busses. Why don't we have two pin types that correspond? _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
