DJ Delorie wrote:
I published my paper mostly to get a discussion going on what busses *mean* though, not the implementation details. For example, what does it mean when three busses with different names are connected?D[15:0] ======**==== D[15:0] || \\==== A[1:16] With nets, it breaks if you do that. I would want DRC to complain to - it's a real error to give one signal two names. Do we need a separate "bus thing" in order to apply different rules?
I don't think that's needed, but maybe a short version of a bus name would be handy when a big bus of 70 wires is referred to because it has some reason to exist as a group. How I would name the above case to get a decisive result is D[15:0],A[1:16] with a branch called A[1:16]
And I want to understand the implications of pins that reflect multiple signals, too - mapping names and numbers, etc.
To me, pins can be handled the same as bus names. a "pin" named D[15:0] can be used to generate all details necessary for netlisting and module hookup. When I say modules, I'm thinking in verilog, where a port corresponds to a "pin", and a port can be multiwire. Or, you could define pin as single wire and create a new thing called a port, that has multiwire function. verilog-ams-heads would know what you mean already. -- Ecosensory Austin TX tinyOS devel on: ubuntu Linux; tinyOS v2.0.2; telosb ecosens1 _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
