On 11/06/2010 10:16 PM, John Griessen wrote:
begin at posedge delay # 40 assign A + B or C --> mcu_cson end
Should be more like: at posedge clock1 delay # 40 begin assign A + B or C --> mcu_cson assign A . D --> mcu_wron end at posedge clock1 delay # 60 begin assign E . A --> mcu_wron end That is to get functions of instructions or whatever triggers your event, then add different delays to different wires. Each variable above could be a vector such as: mcu_wron[15:0] mcu_wron[15:0] D[15:0] Some of your triggers are going to come from one wire. There's a shorthand for extending one bit into as many as you want -- forgot it... do that with the one bit signal before anding it with something to trigger a word transition by the assign statement. I doubt your really want anything recursive. Everything that's a primitive function in verilog happens in parallel all the time, not as a procedure. John G _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
