Lars Segerlund wrote:
I am trying to synthesice a simple adder, and I am getting errors like
this.
Does anybody know whats going wrong ?
module addc(A, B, CIN, COUT, Q);
input A, B, CIN;
output COUT, Q;
assign Q=A ^ B ^ CIN;
assign COUT= (A & B) | (A & CIN) | (B & CIN);
endmodule
bash-2.05b$ ../tools/bin/iverilog -S addc.v
Passes
bash-2.05b$ ../tools/bin/iverilog -tfpga addc.v
UNSUPPORTED LOGIC TYPE: 19
UNSUPPORTED LOGIC TYPE: 19
UNSUPPORTED LOGIC TYPE: 1
UNSUPPORTED LOGIC TYPE: 1
UNSUPPORTED LOGIC TYPE: 1
Including the version would help. However, I can tell you
that those are AND and XOR gates that that particular code
generator doesn't support yet. Try for example -tfpga -farch=virtex
and see an improvement.
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
