Thanks,
The same works for me, now I probably have to look at the source a bit :-( ....
I was trying to use the lpm target, but I don't know if this is the correct way ?
This is from the file fpga.txt in the source ...
The following is a list of architecture types that this code generator supports.
* arch=lpm
This is a device independent format, where the gates are device types as defined by the LPM 2 1 0 specification. Some backend tools may take this format, or users may write interface libraries to connect these netlists to the device in question.
And here is th result of :
bash-2.05b$ iverilog -tfpga -parch=lpm addc.v Unknown architecture arch=lpm error: Code generation had errors. bash-2.05b$
So I think I have to look a bit futher.
/ Lars Segerlund.
Stephen Williams wrote:
Lars Segerlund wrote:
I am trying to synthesice a simple adder, and I am getting errors like this.
Does anybody know whats going wrong ?
module addc(A, B, CIN, COUT, Q); input A, B, CIN; output COUT, Q; assign Q=A ^ B ^ CIN; assign COUT= (A & B) | (A & CIN) | (B & CIN); endmodule
bash-2.05b$ ../tools/bin/iverilog -S addc.v
Passes
bash-2.05b$ ../tools/bin/iverilog -tfpga addc.v UNSUPPORTED LOGIC TYPE: 19 UNSUPPORTED LOGIC TYPE: 19 UNSUPPORTED LOGIC TYPE: 1 UNSUPPORTED LOGIC TYPE: 1 UNSUPPORTED LOGIC TYPE: 1
Including the version would help. However, I can tell you that those are AND and XOR gates that that particular code generator doesn't support yet. Try for example -tfpga -farch=virtex and see an improvement.
