On Tuesday 04 November 2003 02:40, Bill Cox wrote: > -- Schematic generator from structural Verilog/VHDL. �It could take > output from Icarus Verilog and generate .sch and .sym files. �It could > also possibly generate schematics from the structural portions of RTL > level Verilog
If you could make geda into something like VisualHDL? At least being able to read in the interfaces of RTL in text files and modify the symbols according to added pins etc. VHDL is a real pain when it comes to connecting all those ports. > -- A netlist translation capability: �Verilog/VHDL/SPICE both in and out > so we can convert from one to the other. You want to translate spice into schematic, maybe. That is a killer app. No free tool has this possibility. I have used Spicevision and I have no possibility to edit the schematic. It is only a viewer. I suggest a stupid placement engine and then the user can optimize it by hand if he cares. The modified view can be saved for later use. If the source spice change, the changes are highlighted, additional elements are added to an edge for placement. Excelent app for designers cooperatin with different tools. > -- A hierarchy viewer, preferably integrated with gschem. �This would > initially support net highlighting and instance/net finding. �If > integration is hard, a gschem-like viewer could be written, without > editing capabilities. If one could build virtual hierarchies out of a pool of schematics that would be great. Then one could start a top down design with lots of black boxes filled with rtl and at a later stage insert a synthesized netlist in its place without needing to delete the original sheet. This is maybe something like configurations in cadence, but it has its limits. It would also be excelent for revision management: If a page has to be changed, make a copy of it under another name, make the changes, attach it into the virtual tree, make a new make a new config as a copy of the old and in this config replace the old page with the new. This way you keep all schematics as they were and you can generate a netlist for the old board by using the old config for the netlister or you can make a new revised netlist by using the new config. With a virtual tree one could also include schematics in the hierarchy that are located elsewhere on the disk. Excelent for team work. > -- A PCB place and route tool I would rather see tight integration with magic VLSI. > -- A simple router to help gschem make rectilinear routing changes after > a move operation. Just don't make it like cadence composer. How about integrating the simulation results so that nets can be annotated with labels that retreive data from the simulation database? My no 1 wish is the SPICE to schematics converter. -- Svenn
