It's valid verilog, but kind-of a weird device you are modeling there. Are you really trying to make a D-type flip-flop that loads on both edges of the clock input? The Icarus Verilog synth- esizer doesn't quite know what to make of it, so it leaves it as behavioral code.
I'm not actually trying to make a DFF, thats just some code that shows the error. Are you saying that icarus can't handle circuits that are sensitive to both edges of a signal? Are there other cases when I would see that error message? Thanks for your insitghts.
-d
